| 430 | } |
| 431 | |
| 432 | static void |
| 433 | mv_watchdog_disable_armv5(void) |
| 434 | { |
| 435 | uint32_t val, irq_cause,irq_mask; |
| 436 | |
| 437 | val = mv_get_timer_control(); |
| 438 | val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); |
| 439 | mv_set_timer_control(val); |
| 440 | |
| 441 | val = read_cpu_ctrl(RSTOUTn_MASK); |
| 442 | val &= ~WD_RST_OUT_EN; |
| 443 | write_cpu_ctrl(RSTOUTn_MASK, val); |
| 444 | |
| 445 | irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); |
| 446 | irq_mask &= ~(IRQ_TIMER_WD_MASK); |
| 447 | write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); |
| 448 | |
| 449 | irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); |
| 450 | irq_cause &= timer_softc->config->irq_timer_wd_clr; |
| 451 | write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); |
| 452 | } |
| 453 | |
| 454 | static void |
| 455 | mv_watchdog_disable_armadaxp(void) |
nothing calls this directly
no test coverage detected