| 452 | } |
| 453 | |
| 454 | static void |
| 455 | mv_watchdog_disable_armadaxp(void) |
| 456 | { |
| 457 | uint32_t val, irq_cause; |
| 458 | |
| 459 | val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); |
| 460 | val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); |
| 461 | write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); |
| 462 | |
| 463 | val = read_cpu_misc(RSTOUTn_MASK_ARMV7); |
| 464 | val |= RSTOUTn_MASK_WD; |
| 465 | write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); |
| 466 | |
| 467 | irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); |
| 468 | irq_cause &= timer_softc->config->irq_timer_wd_clr; |
| 469 | write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); |
| 470 | |
| 471 | val = mv_get_timer_control(); |
| 472 | val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); |
| 473 | mv_set_timer_control(val); |
| 474 | } |
| 475 | |
| 476 | /* |
| 477 | * Watchdog event handler. |
nothing calls this directly
no test coverage detected