| 110 | #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) |
| 111 | |
| 112 | static __inline uint32_t |
| 113 | __set_cpsr(uint32_t bic, uint32_t eor) |
| 114 | { |
| 115 | uint32_t tmp, ret; |
| 116 | |
| 117 | __asm __volatile( |
| 118 | "mrs %0, cpsr\n" /* Get the CPSR */ |
| 119 | "bic %1, %0, %2\n" /* Clear bits */ |
| 120 | "eor %1, %1, %3\n" /* XOR bits */ |
| 121 | "msr cpsr_xc, %1\n" /* Set the CPSR */ |
| 122 | : "=&r" (ret), "=&r" (tmp) |
| 123 | : "r" (bic), "r" (eor) : "memory"); |
| 124 | |
| 125 | return ret; |
| 126 | } |
| 127 | |
| 128 | static __inline uint32_t |
| 129 | disable_interrupts(uint32_t mask) |
no outgoing calls
no test coverage detected