| 420 | } |
| 421 | |
| 422 | static __inline void |
| 423 | tlb_flush_range(vm_offset_t va, vm_size_t size) |
| 424 | { |
| 425 | vm_offset_t eva = va + size; |
| 426 | |
| 427 | KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); |
| 428 | KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__, |
| 429 | size)); |
| 430 | |
| 431 | dsb(); |
| 432 | ARM_SMP_UP( |
| 433 | { |
| 434 | for (; va < eva; va += PAGE_SIZE) |
| 435 | _CP15_TLBIMVAAIS(va); |
| 436 | }, |
| 437 | { |
| 438 | for (; va < eva; va += PAGE_SIZE) |
| 439 | _CP15_TLBIMVA(va | CPU_ASID_KERNEL); |
| 440 | } |
| 441 | ); |
| 442 | dsb(); |
| 443 | } |
| 444 | #else /* __ARM_ARCH < 7 */ |
| 445 | |
| 446 | #define tlb_flush_all() tlb_flush_all_local() |
no outgoing calls
no test coverage detected