Write back and invalidate D-cache to PoC */
| 599 | |
| 600 | /* Write back and invalidate D-cache to PoC */ |
| 601 | static __inline void |
| 602 | dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) |
| 603 | { |
| 604 | vm_offset_t va; |
| 605 | vm_offset_t eva = sva + size; |
| 606 | |
| 607 | dsb(); |
| 608 | /* write back L1 first */ |
| 609 | va = sva & ~cpuinfo.dcache_line_mask; |
| 610 | for ( ; va < eva; va += cpuinfo.dcache_line_size) { |
| 611 | _CP15_DCCMVAC(va); |
| 612 | } |
| 613 | dsb(); |
| 614 | |
| 615 | /* then write back and invalidate L2 */ |
| 616 | cpu_l2cache_wbinv_range(pa, size); |
| 617 | |
| 618 | /* then invalidate L1 */ |
| 619 | va = sva & ~cpuinfo.dcache_line_mask; |
| 620 | for ( ; va < eva; va += cpuinfo.dcache_line_size) { |
| 621 | _CP15_DCIMVAC(va); |
| 622 | } |
| 623 | dsb(); |
| 624 | } |
| 625 | |
| 626 | /* Set TTB0 register */ |
| 627 | static __inline void |
no outgoing calls
no test coverage detected