* Discard D-cache lines to PoC, prior to overwrite by DMA engine. * * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't * flow into L1 while invalidating. This routine is intended to be used only * when invalidating a buffer before a DMA operation loads new data into memory. * The concern in this case is that dirty lines are not evicted to main memory, * overwrit
| 559 | * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned. |
| 560 | */ |
| 561 | static __inline void |
| 562 | dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size) |
| 563 | { |
| 564 | vm_offset_t eva = va + size; |
| 565 | |
| 566 | /* invalidate L1 first */ |
| 567 | dsb(); |
| 568 | va &= ~cpuinfo.dcache_line_mask; |
| 569 | for ( ; va < eva; va += cpuinfo.dcache_line_size) { |
| 570 | _CP15_DCIMVAC(va); |
| 571 | } |
| 572 | dsb(); |
| 573 | |
| 574 | /* then L2 */ |
| 575 | cpu_l2cache_inv_range(pa, size); |
| 576 | } |
| 577 | |
| 578 | /* |
| 579 | * Write back D-cache to PoC |
no outgoing calls
no test coverage detected