| 471 | } |
| 472 | |
| 473 | static int |
| 474 | pl310_attach(device_t dev) |
| 475 | { |
| 476 | struct pl310_softc *sc = device_get_softc(dev); |
| 477 | int rid; |
| 478 | uint32_t cache_id, debug_ctrl; |
| 479 | phandle_t node; |
| 480 | |
| 481 | sc->sc_dev = dev; |
| 482 | rid = 0; |
| 483 | sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, |
| 484 | RF_ACTIVE); |
| 485 | if (sc->sc_mem_res == NULL) |
| 486 | panic("%s: Cannot map registers", device_get_name(dev)); |
| 487 | |
| 488 | /* Allocate an IRQ resource */ |
| 489 | rid = 0; |
| 490 | sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
| 491 | RF_ACTIVE | RF_SHAREABLE); |
| 492 | if (sc->sc_irq_res == NULL) { |
| 493 | device_printf(dev, "cannot allocate IRQ, not using interrupt\n"); |
| 494 | } |
| 495 | |
| 496 | pl310_softc = sc; |
| 497 | mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN); |
| 498 | |
| 499 | cache_id = pl310_read4(sc, PL310_CACHE_ID); |
| 500 | sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) & |
| 501 | CACHE_ID_RELEASE_MASK; |
| 502 | device_printf(dev, "Part number: 0x%x, release: 0x%x\n", |
| 503 | (cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK, |
| 504 | (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK); |
| 505 | |
| 506 | /* |
| 507 | * Test for "arm,io-coherent" property and disable sync operation if |
| 508 | * platform is I/O coherent. Outer sync operations are not needed |
| 509 | * on coherent platform and may be harmful in certain situations. |
| 510 | */ |
| 511 | node = ofw_bus_get_node(dev); |
| 512 | if (OF_hasprop(node, "arm,io-coherent")) |
| 513 | sc->sc_io_coherent = true; |
| 514 | |
| 515 | /* |
| 516 | * If L2 cache is already enabled then something has violated the rules, |
| 517 | * because caches are supposed to be off at kernel entry. The cache |
| 518 | * must be disabled to write the configuration registers without |
| 519 | * triggering an access error (SLVERR), but there's no documented safe |
| 520 | * procedure for disabling the L2 cache in the manual. So we'll try to |
| 521 | * invent one: |
| 522 | * - Use the debug register to force write-through mode and prevent |
| 523 | * linefills (allocation of new lines on read); now anything we do |
| 524 | * will not cause new data to come into the L2 cache. |
| 525 | * - Writeback and invalidate the current contents. |
| 526 | * - Disable the controller. |
| 527 | * - Restore the original debug settings. |
| 528 | */ |
| 529 | if (pl310_read4(sc, PL310_CTRL) & CTRL_ENABLED) { |
| 530 | device_printf(dev, "Warning: L2 Cache should not already be " |
nothing calls this directly
no test coverage detected