| 238 | } |
| 239 | |
| 240 | static void |
| 241 | ipi_stop(void *dummy __unused) |
| 242 | { |
| 243 | u_int cpu; |
| 244 | |
| 245 | /* |
| 246 | * IPI_STOP_HARD is mapped to IPI_STOP. |
| 247 | */ |
| 248 | CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); |
| 249 | |
| 250 | cpu = PCPU_GET(cpuid); |
| 251 | savectx(&stoppcbs[cpu]); |
| 252 | |
| 253 | /* |
| 254 | * CPUs are stopped when entering the debugger and at |
| 255 | * system shutdown, both events which can precede a |
| 256 | * panic dump. For the dump to be correct, all caches |
| 257 | * must be flushed and invalidated, but on ARM there's |
| 258 | * no way to broadcast a wbinv_all to other cores. |
| 259 | * Instead, we have each core do the local wbinv_all as |
| 260 | * part of stopping the core. The core requesting the |
| 261 | * stop will do the l2 cache flush after all other cores |
| 262 | * have done their l1 flushes and stopped. |
| 263 | */ |
| 264 | dcache_wbinv_poc_all(); |
| 265 | |
| 266 | /* Indicate we are stopped */ |
| 267 | CPU_SET_ATOMIC(cpu, &stopped_cpus); |
| 268 | |
| 269 | /* Wait for restart */ |
| 270 | while (!CPU_ISSET(cpu, &started_cpus)) |
| 271 | cpu_spinwait(); |
| 272 | |
| 273 | CPU_CLR_ATOMIC(cpu, &started_cpus); |
| 274 | CPU_CLR_ATOMIC(cpu, &stopped_cpus); |
| 275 | #ifdef DDB |
| 276 | dbg_resume_dbreg(); |
| 277 | #endif |
| 278 | CTR0(KTR_SMP, "IPI_STOP (restart)"); |
| 279 | } |
| 280 | |
| 281 | static void |
| 282 | ipi_preempt(void *arg) |
nothing calls this directly
no test coverage detected