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Function print_v7_cache

freebsd/arm/arm/identcpu-v6.c:190–253  ·  view source on GitHub ↗

Source from the content-addressed store, hash-verified

188}
189
190static void
191print_v7_cache(void )
192{
193 uint32_t type, val, size, sets, ways, linesize;
194 int i;
195
196 printf("LoUU:%d LoC:%d LoUIS:%d \n",
197 CPU_CLIDR_LOUU(cpuinfo.clidr) + 1,
198 CPU_CLIDR_LOC(cpuinfo.clidr) + 1,
199 CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1);
200
201 for (i = 0; i < 7; i++) {
202 type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i);
203 if (type == 0)
204 break;
205 printf("Cache level %d:\n", i + 1);
206 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
207 type == CACHE_SEP_CACHE) {
208 cp15_csselr_set(i << 1);
209 val = cp15_ccsidr_get();
210 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
211 sets = CPUV7_CT_xSIZE_SET(val) + 1;
212 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
213 size = (ways * sets * linesize) / 1024;
214
215 if (type == CACHE_UNI_CACHE)
216 printf(" %dKB/%dB %d-way unified cache",
217 size, linesize,ways);
218 else
219 printf(" %dKB/%dB %d-way data cache",
220 size, linesize, ways);
221 if (val & CPUV7_CT_CTYPE_WT)
222 printf(" WT");
223 if (val & CPUV7_CT_CTYPE_WB)
224 printf(" WB");
225 if (val & CPUV7_CT_CTYPE_RA)
226 printf(" Read-Alloc");
227 if (val & CPUV7_CT_CTYPE_WA)
228 printf(" Write-Alloc");
229 printf("\n");
230 }
231
232 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
233 cp15_csselr_set(i << 1 | 1);
234 val = cp15_ccsidr_get();
235 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1;
236 sets = CPUV7_CT_xSIZE_SET(val) + 1;
237 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4);
238 size = (ways * sets * linesize) / 1024;
239 printf(" %dKB/%dB %d-way instruction cache",
240 size, linesize, ways);
241 if (val & CPUV7_CT_CTYPE_WT)
242 printf(" WT");
243 if (val & CPUV7_CT_CTYPE_WB)
244 printf(" WB");
245 if (val & CPUV7_CT_CTYPE_RA)
246 printf(" Read-Alloc");
247 if (val & CPUV7_CT_CTYPE_WA)

Callers 1

identify_arm_cpuFunction · 0.85

Calls 1

printfFunction · 0.50

Tested by

no test coverage detected