| 108 | }; |
| 109 | |
| 110 | static void |
| 111 | print_v5_cache(void) |
| 112 | { |
| 113 | uint32_t isize, dsize; |
| 114 | uint32_t multiplier; |
| 115 | int pcache_type; |
| 116 | int pcache_unified; |
| 117 | int picache_size; |
| 118 | int picache_line_size; |
| 119 | int picache_ways; |
| 120 | int pdcache_size; |
| 121 | int pdcache_line_size; |
| 122 | int pdcache_ways; |
| 123 | |
| 124 | pcache_unified = 0; |
| 125 | picache_size = 0 ; |
| 126 | picache_line_size = 0 ; |
| 127 | picache_ways = 0 ; |
| 128 | pdcache_size = 0; |
| 129 | pdcache_line_size = 0; |
| 130 | pdcache_ways = 0; |
| 131 | |
| 132 | if ((cpuinfo.ctr & CPU_CT_S) == 0) |
| 133 | pcache_unified = 1; |
| 134 | |
| 135 | /* |
| 136 | * If you want to know how this code works, go read the ARM ARM. |
| 137 | */ |
| 138 | pcache_type = CPU_CT_CTYPE(cpuinfo.ctr); |
| 139 | |
| 140 | if (pcache_unified == 0) { |
| 141 | isize = CPU_CT_ISIZE(cpuinfo.ctr); |
| 142 | multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; |
| 143 | picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); |
| 144 | if (CPU_CT_xSIZE_ASSOC(isize) == 0) { |
| 145 | if (isize & CPU_CT_xSIZE_M) |
| 146 | picache_line_size = 0; /* not present */ |
| 147 | else |
| 148 | picache_ways = 1; |
| 149 | } else { |
| 150 | picache_ways = multiplier << |
| 151 | (CPU_CT_xSIZE_ASSOC(isize) - 1); |
| 152 | } |
| 153 | picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); |
| 154 | } |
| 155 | |
| 156 | dsize = CPU_CT_DSIZE(cpuinfo.ctr); |
| 157 | multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; |
| 158 | pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); |
| 159 | if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { |
| 160 | if (dsize & CPU_CT_xSIZE_M) |
| 161 | pdcache_line_size = 0; /* not present */ |
| 162 | else |
| 163 | pdcache_ways = 1; |
| 164 | } else { |
| 165 | pdcache_ways = multiplier << |
| 166 | (CPU_CT_xSIZE_ASSOC(dsize) - 1); |
| 167 | } |
no test coverage detected