| 286 | static void disassemble_printaddr(u_int address); |
| 287 | |
| 288 | vm_offset_t |
| 289 | disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt) |
| 290 | { |
| 291 | const struct arm32_insn *i_ptr = arm32_i; |
| 292 | |
| 293 | u_int insn; |
| 294 | int matchp; |
| 295 | int branch; |
| 296 | char* f_ptr; |
| 297 | int fmt; |
| 298 | |
| 299 | fmt = 0; |
| 300 | matchp = 0; |
| 301 | insn = di->di_readword(loc); |
| 302 | |
| 303 | /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ |
| 304 | |
| 305 | while (i_ptr->name) { |
| 306 | if ((insn & i_ptr->mask) == i_ptr->pattern) { |
| 307 | matchp = 1; |
| 308 | break; |
| 309 | } |
| 310 | i_ptr++; |
| 311 | } |
| 312 | |
| 313 | if (!matchp) { |
| 314 | di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); |
| 315 | return(loc + INSN_SIZE); |
| 316 | } |
| 317 | |
| 318 | /* If instruction forces condition code, don't print it. */ |
| 319 | if ((i_ptr->mask & 0xf0000000) == 0xf0000000) |
| 320 | di->di_printf("%s", i_ptr->name); |
| 321 | else |
| 322 | di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); |
| 323 | |
| 324 | f_ptr = i_ptr->format; |
| 325 | |
| 326 | /* Insert tab if there are no instruction modifiers */ |
| 327 | |
| 328 | if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { |
| 329 | ++fmt; |
| 330 | di->di_printf("\t"); |
| 331 | } |
| 332 | |
| 333 | while (*f_ptr) { |
| 334 | switch (*f_ptr) { |
| 335 | /* 2 - print Operand 2 of a data processing instruction */ |
| 336 | case '2': |
| 337 | if (insn & 0x02000000) { |
| 338 | int rotate= ((insn >> 7) & 0x1e); |
| 339 | |
| 340 | di->di_printf("#0x%08x", |
| 341 | (insn & 0xff) << (32 - rotate) | |
| 342 | (insn & 0xff) >> rotate); |
| 343 | } else { |
| 344 | disasm_register_shift(di, insn); |
| 345 | } |
no test coverage detected