| 421 | } |
| 422 | |
| 423 | void |
| 424 | dbg_show_watchpoint(void) |
| 425 | { |
| 426 | uint32_t wcr, len, type; |
| 427 | uint32_t addr; |
| 428 | boolean_t is_enabled; |
| 429 | int i; |
| 430 | |
| 431 | if (!dbg_capable()) { |
| 432 | db_printf("Architecture does not support HW " |
| 433 | "breakpoints/watchpoints\n"); |
| 434 | return; |
| 435 | } |
| 436 | |
| 437 | db_printf("\nhardware watchpoints:\n"); |
| 438 | db_printf(" watch status type len address symbol\n"); |
| 439 | db_printf(" ----- -------- ---------- --- ---------- ------------------\n"); |
| 440 | for (i = 0; i < dbg_watchpoint_num; i++) { |
| 441 | wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i); |
| 442 | if ((wcr & DBG_WB_CTRL_E) != 0) |
| 443 | is_enabled = TRUE; |
| 444 | else |
| 445 | is_enabled = FALSE; |
| 446 | |
| 447 | type = DBG_WB_CTRL_ACCESS_MASK(wcr); |
| 448 | len = DBG_WB_CTRL_LEN_MASK(wcr); |
| 449 | addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i) & DBGWVR_ADDR_MASK; |
| 450 | db_printf(" %-5d %-8s %10s %3d 0x%08x ", i, |
| 451 | is_enabled ? "enabled" : "disabled", |
| 452 | is_enabled ? dbg_watchtype_str(type) : "", |
| 453 | is_enabled ? dbg_watchtype_len(len) : 0, |
| 454 | addr); |
| 455 | db_printsym((db_addr_t)addr, DB_STGY_ANY); |
| 456 | db_printf("\n"); |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | static boolean_t |
| 461 | dbg_check_slot_free(enum dbg_t type, u_int slot) |
no test coverage detected