| 701 | } |
| 702 | |
| 703 | static void |
| 704 | emac_intr(void *arg) |
| 705 | { |
| 706 | struct emac_softc *sc; |
| 707 | struct ifnet *ifp; |
| 708 | uint32_t reg_val; |
| 709 | |
| 710 | sc = (struct emac_softc *)arg; |
| 711 | EMAC_LOCK(sc); |
| 712 | |
| 713 | /* Disable all interrupts */ |
| 714 | EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); |
| 715 | /* Get EMAC interrupt status */ |
| 716 | reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); |
| 717 | /* Clear ISR status */ |
| 718 | EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); |
| 719 | |
| 720 | /* Received incoming packet */ |
| 721 | if (reg_val & EMAC_INT_STA_RX) |
| 722 | emac_rxeof(sc, sc->emac_rx_process_limit); |
| 723 | |
| 724 | /* Transmit Interrupt check */ |
| 725 | if (reg_val & EMAC_INT_STA_TX) { |
| 726 | emac_txeof(sc, reg_val); |
| 727 | ifp = sc->emac_ifp; |
| 728 | if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) |
| 729 | emac_start_locked(ifp); |
| 730 | } |
| 731 | |
| 732 | /* Re-enable interrupt mask */ |
| 733 | reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); |
| 734 | reg_val |= EMAC_INT_EN; |
| 735 | EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); |
| 736 | EMAC_UNLOCK(sc); |
| 737 | } |
| 738 | |
| 739 | static int |
| 740 | emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) |
nothing calls this directly
no test coverage detected