| 501 | } |
| 502 | |
| 503 | static void |
| 504 | emac_init_locked(struct emac_softc *sc) |
| 505 | { |
| 506 | struct ifnet *ifp; |
| 507 | struct mii_data *mii; |
| 508 | uint32_t reg_val; |
| 509 | uint8_t *eaddr; |
| 510 | |
| 511 | EMAC_ASSERT_LOCKED(sc); |
| 512 | |
| 513 | ifp = sc->emac_ifp; |
| 514 | if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) |
| 515 | return; |
| 516 | |
| 517 | /* Flush RX FIFO */ |
| 518 | reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); |
| 519 | reg_val |= EMAC_RX_FLUSH_FIFO; |
| 520 | EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); |
| 521 | DELAY(1); |
| 522 | |
| 523 | /* Soft reset MAC */ |
| 524 | reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); |
| 525 | reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); |
| 526 | EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); |
| 527 | |
| 528 | /* Set MII clock */ |
| 529 | reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); |
| 530 | reg_val &= (~(0xf << 2)); |
| 531 | reg_val |= (0xd << 2); |
| 532 | EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); |
| 533 | |
| 534 | /* Clear RX counter */ |
| 535 | EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); |
| 536 | |
| 537 | /* Disable all interrupt and clear interrupt status */ |
| 538 | EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); |
| 539 | reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); |
| 540 | EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); |
| 541 | DELAY(1); |
| 542 | |
| 543 | /* Set up TX */ |
| 544 | reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); |
| 545 | reg_val |= EMAC_TX_AB_M; |
| 546 | reg_val &= EMAC_TX_TM; |
| 547 | EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); |
| 548 | |
| 549 | /* Set up RX */ |
| 550 | reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); |
| 551 | reg_val |= EMAC_RX_SETUP; |
| 552 | reg_val &= EMAC_RX_TM; |
| 553 | EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); |
| 554 | |
| 555 | /* Set up MAC CTL0. */ |
| 556 | reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); |
| 557 | reg_val |= EMAC_MAC_CTL0_SETUP; |
| 558 | EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); |
| 559 | |
| 560 | /* Set up MAC CTL1. */ |
no test coverage detected