| 863 | } |
| 864 | |
| 865 | static void |
| 866 | aw_mmc_req_done(struct aw_mmc_softc *sc) |
| 867 | { |
| 868 | struct mmc_command *cmd; |
| 869 | #ifdef MMCCAM |
| 870 | union ccb *ccb; |
| 871 | #else |
| 872 | struct mmc_request *req; |
| 873 | #endif |
| 874 | uint32_t val, mask; |
| 875 | int retry; |
| 876 | |
| 877 | #ifdef MMCCAM |
| 878 | ccb = sc->ccb; |
| 879 | cmd = &ccb->mmcio.cmd; |
| 880 | #else |
| 881 | cmd = sc->aw_req->cmd; |
| 882 | #endif |
| 883 | if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { |
| 884 | device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); |
| 885 | } |
| 886 | if (cmd->error != MMC_ERR_NONE) { |
| 887 | /* Reset the FIFO and DMA engines. */ |
| 888 | mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; |
| 889 | val = AW_MMC_READ_4(sc, AW_MMC_GCTL); |
| 890 | AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); |
| 891 | |
| 892 | retry = AW_MMC_RESET_RETRY; |
| 893 | while (--retry > 0) { |
| 894 | if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & |
| 895 | AW_MMC_GCTL_RESET) == 0) |
| 896 | break; |
| 897 | DELAY(100); |
| 898 | } |
| 899 | if (retry == 0) |
| 900 | device_printf(sc->aw_dev, |
| 901 | "timeout resetting DMA/FIFO\n"); |
| 902 | aw_mmc_update_clock(sc, 1); |
| 903 | } |
| 904 | |
| 905 | callout_stop(&sc->aw_timeoutc); |
| 906 | sc->aw_intr = 0; |
| 907 | sc->aw_resid = 0; |
| 908 | sc->aw_dma_map_err = 0; |
| 909 | sc->aw_intr_wait = 0; |
| 910 | #ifdef MMCCAM |
| 911 | sc->ccb = NULL; |
| 912 | ccb->ccb_h.status = |
| 913 | (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); |
| 914 | xpt_done(ccb); |
| 915 | #else |
| 916 | req = sc->aw_req; |
| 917 | sc->aw_req = NULL; |
| 918 | req->done(req); |
| 919 | #endif |
| 920 | } |
| 921 | |
| 922 | static void |
no test coverage detected