| 824 | } |
| 825 | |
| 826 | static int |
| 827 | aw_mmc_init(struct aw_mmc_softc *sc) |
| 828 | { |
| 829 | uint32_t reg; |
| 830 | int ret; |
| 831 | |
| 832 | ret = aw_mmc_reset(sc); |
| 833 | if (ret != 0) |
| 834 | return (ret); |
| 835 | |
| 836 | /* Set the timeout. */ |
| 837 | AW_MMC_WRITE_4(sc, AW_MMC_TMOR, |
| 838 | AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | |
| 839 | AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); |
| 840 | |
| 841 | /* Unmask interrupts. */ |
| 842 | AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); |
| 843 | |
| 844 | /* Clear pending interrupts. */ |
| 845 | AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); |
| 846 | |
| 847 | /* Debug register, undocumented */ |
| 848 | AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); |
| 849 | |
| 850 | /* Function select register */ |
| 851 | AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); |
| 852 | |
| 853 | AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); |
| 854 | |
| 855 | /* Enable interrupts and disable AHB access. */ |
| 856 | reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); |
| 857 | reg |= AW_MMC_GCTL_INT_ENB; |
| 858 | reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; |
| 859 | reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; |
| 860 | AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); |
| 861 | |
| 862 | return (0); |
| 863 | } |
| 864 | |
| 865 | static void |
| 866 | aw_mmc_req_done(struct aw_mmc_softc *sc) |
no test coverage detected