| 1363 | } |
| 1364 | |
| 1365 | int |
| 1366 | vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset) |
| 1367 | { |
| 1368 | int error; |
| 1369 | |
| 1370 | if ((vmx->cap[vcpu].proc_ctls & PROCBASED_TSC_OFFSET) == 0) { |
| 1371 | vmx->cap[vcpu].proc_ctls |= PROCBASED_TSC_OFFSET; |
| 1372 | vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls); |
| 1373 | VCPU_CTR0(vmx->vm, vcpu, "Enabling TSC offsetting"); |
| 1374 | } |
| 1375 | |
| 1376 | error = vmwrite(VMCS_TSC_OFFSET, offset); |
| 1377 | #ifdef BHYVE_SNAPSHOT |
| 1378 | if (error == 0) |
| 1379 | error = vm_set_tsc_offset(vmx->vm, vcpu, offset); |
| 1380 | #endif |
| 1381 | return (error); |
| 1382 | } |
| 1383 | |
| 1384 | #define NMI_BLOCKING (VMCS_INTERRUPTIBILITY_NMI_BLOCKING | \ |
| 1385 | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING) |
no test coverage detected