| 1141 | #define EFER_MBZ_BITS 0xFFFFFFFFFFFF0200UL |
| 1142 | |
| 1143 | static int |
| 1144 | svm_write_efer(struct svm_softc *sc, int vcpu, uint64_t newval, bool *retu) |
| 1145 | { |
| 1146 | struct vm_exit *vme; |
| 1147 | struct vmcb_state *state; |
| 1148 | uint64_t changed, lma, oldval; |
| 1149 | int error; |
| 1150 | |
| 1151 | state = svm_get_vmcb_state(sc, vcpu); |
| 1152 | |
| 1153 | oldval = state->efer; |
| 1154 | VCPU_CTR2(sc->vm, vcpu, "wrmsr(efer) %#lx/%#lx", oldval, newval); |
| 1155 | |
| 1156 | newval &= ~0xFE; /* clear the Read-As-Zero (RAZ) bits */ |
| 1157 | changed = oldval ^ newval; |
| 1158 | |
| 1159 | if (newval & EFER_MBZ_BITS) |
| 1160 | goto gpf; |
| 1161 | |
| 1162 | /* APMv2 Table 14-5 "Long-Mode Consistency Checks" */ |
| 1163 | if (changed & EFER_LME) { |
| 1164 | if (state->cr0 & CR0_PG) |
| 1165 | goto gpf; |
| 1166 | } |
| 1167 | |
| 1168 | /* EFER.LMA = EFER.LME & CR0.PG */ |
| 1169 | if ((newval & EFER_LME) != 0 && (state->cr0 & CR0_PG) != 0) |
| 1170 | lma = EFER_LMA; |
| 1171 | else |
| 1172 | lma = 0; |
| 1173 | |
| 1174 | if ((newval & EFER_LMA) != lma) |
| 1175 | goto gpf; |
| 1176 | |
| 1177 | if (newval & EFER_NXE) { |
| 1178 | if (!vm_cpuid_capability(sc->vm, vcpu, VCC_NO_EXECUTE)) |
| 1179 | goto gpf; |
| 1180 | } |
| 1181 | |
| 1182 | /* |
| 1183 | * XXX bhyve does not enforce segment limits in 64-bit mode. Until |
| 1184 | * this is fixed flag guest attempt to set EFER_LMSLE as an error. |
| 1185 | */ |
| 1186 | if (newval & EFER_LMSLE) { |
| 1187 | vme = vm_exitinfo(sc->vm, vcpu); |
| 1188 | vm_exit_svm(vme, VMCB_EXIT_MSR, 1, 0); |
| 1189 | *retu = true; |
| 1190 | return (0); |
| 1191 | } |
| 1192 | |
| 1193 | if (newval & EFER_FFXSR) { |
| 1194 | if (!vm_cpuid_capability(sc->vm, vcpu, VCC_FFXSR)) |
| 1195 | goto gpf; |
| 1196 | } |
| 1197 | |
| 1198 | if (newval & EFER_TCE) { |
| 1199 | if (!vm_cpuid_capability(sc->vm, vcpu, VCC_TCE)) |
| 1200 | goto gpf; |
no test coverage detected