| 212 | } |
| 213 | |
| 214 | int |
| 215 | pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) |
| 216 | { |
| 217 | uint32_t val1, val2; |
| 218 | int slot; |
| 219 | |
| 220 | if (!mcfg_enable) |
| 221 | return (0); |
| 222 | |
| 223 | if (minbus != 0) |
| 224 | return (0); |
| 225 | |
| 226 | if (bootverbose) |
| 227 | printf("PCIe: Memory Mapped configuration base @ 0x%lx\n", |
| 228 | base); |
| 229 | |
| 230 | /* XXX: We should make sure this really fits into the direct map. */ |
| 231 | pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20); |
| 232 | pcie_minbus = minbus; |
| 233 | pcie_maxbus = maxbus; |
| 234 | cfgmech = CFGMECH_PCIE; |
| 235 | |
| 236 | /* |
| 237 | * On some AMD systems, some of the devices on bus 0 are |
| 238 | * inaccessible using memory-mapped PCI config access. Walk |
| 239 | * bus 0 looking for such devices. For these devices, we will |
| 240 | * fall back to using type 1 config access instead. |
| 241 | */ |
| 242 | if (pci_cfgregopen() != 0) { |
| 243 | for (slot = 0; slot <= PCI_SLOTMAX; slot++) { |
| 244 | val1 = pcireg_cfgread(0, slot, 0, 0, 4); |
| 245 | if (val1 == 0xffffffff) |
| 246 | continue; |
| 247 | |
| 248 | val2 = pciereg_cfgread(0, slot, 0, 0, 4); |
| 249 | if (val2 != val1) |
| 250 | pcie_badslots |= (1 << slot); |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | return (1); |
| 255 | } |
| 256 | |
| 257 | #define PCIE_VADDR(base, reg, bus, slot, func) \ |
| 258 | ((base) + \ |
nothing calls this directly
no test coverage detected