| 11153 | }; |
| 11154 | |
| 11155 | static void |
| 11156 | sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range, |
| 11157 | vm_offset_t eva) |
| 11158 | { |
| 11159 | const char *mode; |
| 11160 | int i, pat_idx; |
| 11161 | |
| 11162 | if (eva <= range->sva) |
| 11163 | return; |
| 11164 | |
| 11165 | pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true); |
| 11166 | for (i = 0; i < PAT_INDEX_SIZE; i++) |
| 11167 | if (pat_index[i] == pat_idx) |
| 11168 | break; |
| 11169 | |
| 11170 | switch (i) { |
| 11171 | case PAT_WRITE_BACK: |
| 11172 | mode = "WB"; |
| 11173 | break; |
| 11174 | case PAT_WRITE_THROUGH: |
| 11175 | mode = "WT"; |
| 11176 | break; |
| 11177 | case PAT_UNCACHEABLE: |
| 11178 | mode = "UC"; |
| 11179 | break; |
| 11180 | case PAT_UNCACHED: |
| 11181 | mode = "U-"; |
| 11182 | break; |
| 11183 | case PAT_WRITE_PROTECTED: |
| 11184 | mode = "WP"; |
| 11185 | break; |
| 11186 | case PAT_WRITE_COMBINING: |
| 11187 | mode = "WC"; |
| 11188 | break; |
| 11189 | default: |
| 11190 | printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n", |
| 11191 | __func__, pat_idx, range->sva, eva); |
| 11192 | mode = "??"; |
| 11193 | break; |
| 11194 | } |
| 11195 | |
| 11196 | sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n", |
| 11197 | range->sva, eva, |
| 11198 | (range->attrs & X86_PG_RW) != 0 ? 'w' : '-', |
| 11199 | (range->attrs & pg_nx) != 0 ? '-' : 'x', |
| 11200 | (range->attrs & X86_PG_U) != 0 ? 'u' : 's', |
| 11201 | (range->attrs & X86_PG_G) != 0 ? 'g' : '-', |
| 11202 | mode, range->pdpes, range->pdes, range->ptes); |
| 11203 | |
| 11204 | /* Reset to sentinel value. */ |
| 11205 | range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1, |
| 11206 | NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1, |
| 11207 | NPDEPG - 1, NPTEPG - 1); |
| 11208 | } |
| 11209 | |
| 11210 | /* |
| 11211 | * Determine whether the attributes specified by a page table entry match those |
no test coverage detected