| 11004 | } |
| 11005 | |
| 11006 | static void |
| 11007 | pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, |
| 11008 | u_int keyidx) |
| 11009 | { |
| 11010 | pml4_entry_t *pml4e; |
| 11011 | pdp_entry_t *pdpe; |
| 11012 | pd_entry_t newpde, ptpaddr, *pde; |
| 11013 | pt_entry_t newpte, *ptep, pte; |
| 11014 | vm_offset_t va, va_next; |
| 11015 | bool changed; |
| 11016 | |
| 11017 | PMAP_LOCK_ASSERT(pmap, MA_OWNED); |
| 11018 | MPASS(pmap->pm_type == PT_X86); |
| 11019 | MPASS(keyidx <= PMAP_MAX_PKRU_IDX); |
| 11020 | |
| 11021 | for (changed = false, va = sva; va < eva; va = va_next) { |
| 11022 | pml4e = pmap_pml4e(pmap, va); |
| 11023 | if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) { |
| 11024 | va_next = (va + NBPML4) & ~PML4MASK; |
| 11025 | if (va_next < va) |
| 11026 | va_next = eva; |
| 11027 | continue; |
| 11028 | } |
| 11029 | |
| 11030 | pdpe = pmap_pml4e_to_pdpe(pml4e, va); |
| 11031 | if ((*pdpe & X86_PG_V) == 0) { |
| 11032 | va_next = (va + NBPDP) & ~PDPMASK; |
| 11033 | if (va_next < va) |
| 11034 | va_next = eva; |
| 11035 | continue; |
| 11036 | } |
| 11037 | |
| 11038 | va_next = (va + NBPDR) & ~PDRMASK; |
| 11039 | if (va_next < va) |
| 11040 | va_next = eva; |
| 11041 | |
| 11042 | pde = pmap_pdpe_to_pde(pdpe, va); |
| 11043 | ptpaddr = *pde; |
| 11044 | if (ptpaddr == 0) |
| 11045 | continue; |
| 11046 | |
| 11047 | MPASS((ptpaddr & X86_PG_V) != 0); |
| 11048 | if ((ptpaddr & PG_PS) != 0) { |
| 11049 | if (va + NBPDR == va_next && eva >= va_next) { |
| 11050 | newpde = (ptpaddr & ~X86_PG_PKU_MASK) | |
| 11051 | X86_PG_PKU(keyidx); |
| 11052 | if (newpde != ptpaddr) { |
| 11053 | *pde = newpde; |
| 11054 | changed = true; |
| 11055 | } |
| 11056 | continue; |
| 11057 | } else if (!pmap_demote_pde(pmap, pde, va)) { |
| 11058 | continue; |
| 11059 | } |
| 11060 | } |
| 11061 | |
| 11062 | if (va_next > eva) |
| 11063 | va_next = eva; |
no test coverage detected