| 3599 | } |
| 3600 | |
| 3601 | void |
| 3602 | pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva) |
| 3603 | { |
| 3604 | |
| 3605 | pmap_invalidate_cache_range_check_align(sva, eva); |
| 3606 | |
| 3607 | if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) { |
| 3608 | pmap_force_invalidate_cache_range(sva, eva); |
| 3609 | return; |
| 3610 | } |
| 3611 | |
| 3612 | /* See comment in pmap_force_invalidate_cache_range(). */ |
| 3613 | if (pmap_kextract(sva) == lapic_paddr) |
| 3614 | return; |
| 3615 | |
| 3616 | atomic_thread_fence_seq_cst(); |
| 3617 | for (; sva < eva; sva += cpu_clflush_line_size) |
| 3618 | clwb(sva); |
| 3619 | atomic_thread_fence_seq_cst(); |
| 3620 | } |
| 3621 | |
| 3622 | void |
| 3623 | pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr) |
no test coverage detected