* Return > 0 if a hardware breakpoint has been hit, and the * breakpoint was in user space. Return 0, otherwise. */
| 2592 | * breakpoint was in user space. Return 0, otherwise. |
| 2593 | */ |
| 2594 | int |
| 2595 | user_dbreg_trap(register_t dr6) |
| 2596 | { |
| 2597 | u_int64_t dr7; |
| 2598 | u_int64_t bp; /* breakpoint bits extracted from dr6 */ |
| 2599 | int nbp; /* number of breakpoints that triggered */ |
| 2600 | caddr_t addr[4]; /* breakpoint addresses */ |
| 2601 | int i; |
| 2602 | |
| 2603 | bp = dr6 & DBREG_DR6_BMASK; |
| 2604 | if (bp == 0) { |
| 2605 | /* |
| 2606 | * None of the breakpoint bits are set meaning this |
| 2607 | * trap was not caused by any of the debug registers |
| 2608 | */ |
| 2609 | return 0; |
| 2610 | } |
| 2611 | |
| 2612 | dr7 = rdr7(); |
| 2613 | if ((dr7 & 0x000000ff) == 0) { |
| 2614 | /* |
| 2615 | * all GE and LE bits in the dr7 register are zero, |
| 2616 | * thus the trap couldn't have been caused by the |
| 2617 | * hardware debug registers |
| 2618 | */ |
| 2619 | return 0; |
| 2620 | } |
| 2621 | |
| 2622 | nbp = 0; |
| 2623 | |
| 2624 | /* |
| 2625 | * at least one of the breakpoints were hit, check to see |
| 2626 | * which ones and if any of them are user space addresses |
| 2627 | */ |
| 2628 | |
| 2629 | if (bp & 0x01) { |
| 2630 | addr[nbp++] = (caddr_t)rdr0(); |
| 2631 | } |
| 2632 | if (bp & 0x02) { |
| 2633 | addr[nbp++] = (caddr_t)rdr1(); |
| 2634 | } |
| 2635 | if (bp & 0x04) { |
| 2636 | addr[nbp++] = (caddr_t)rdr2(); |
| 2637 | } |
| 2638 | if (bp & 0x08) { |
| 2639 | addr[nbp++] = (caddr_t)rdr3(); |
| 2640 | } |
| 2641 | |
| 2642 | for (i = 0; i < nbp; i++) { |
| 2643 | if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { |
| 2644 | /* |
| 2645 | * addr[i] is in user space |
| 2646 | */ |
| 2647 | return nbp; |
| 2648 | } |
| 2649 | } |
| 2650 | |
| 2651 | /* |