(addr, size)
| 470 | } |
| 471 | |
| 472 | int |
| 473 | db_md_set_watchpoint(addr, size) |
| 474 | db_expr_t addr; |
| 475 | db_expr_t size; |
| 476 | { |
| 477 | struct dbreg *d; |
| 478 | struct pcpu *pc; |
| 479 | int avail, c, cpu, i, wsize; |
| 480 | |
| 481 | d = (struct dbreg *)PCPU_PTR(dbreg); |
| 482 | cpu = PCPU_GET(cpuid); |
| 483 | fill_dbregs(NULL, d); |
| 484 | |
| 485 | avail = 0; |
| 486 | for (i = 0; i < 4; i++) { |
| 487 | if (!DBREG_DR7_ENABLED(d->dr[7], i)) |
| 488 | avail++; |
| 489 | } |
| 490 | |
| 491 | if (avail * 8 < size) |
| 492 | return (-1); |
| 493 | |
| 494 | for (i = 0; i < 4 && size > 0; i++) { |
| 495 | if (!DBREG_DR7_ENABLED(d->dr[7], i)) { |
| 496 | if (size >= 8 || (avail == 1 && size > 4)) |
| 497 | wsize = 8; |
| 498 | else if (size > 2) |
| 499 | wsize = 4; |
| 500 | else |
| 501 | wsize = size; |
| 502 | amd64_set_watch(i, addr, wsize, DBREG_DR7_WRONLY, d); |
| 503 | addr += wsize; |
| 504 | size -= wsize; |
| 505 | avail--; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | set_dbregs(NULL, d); |
| 510 | CPU_FOREACH(c) { |
| 511 | if (c == cpu) |
| 512 | continue; |
| 513 | pc = pcpu_find(c); |
| 514 | memcpy(pc->pc_dbreg, d, sizeof(*d)); |
| 515 | pc->pc_dbreg_cmd = PC_DBREG_CMD_LOAD; |
| 516 | } |
| 517 | |
| 518 | return (0); |
| 519 | } |
| 520 | |
| 521 | int |
| 522 | db_md_clr_watchpoint(addr, size) |
nothing calls this directly
no test coverage detected