| 703 | } |
| 704 | |
| 705 | int |
| 706 | rte_event_port_setup(uint8_t dev_id, uint8_t port_id, |
| 707 | const struct rte_event_port_conf *port_conf) |
| 708 | { |
| 709 | struct rte_eventdev *dev; |
| 710 | struct rte_event_port_conf def_conf; |
| 711 | int diag; |
| 712 | |
| 713 | RTE_EVENTDEV_VALID_DEVID_OR_ERR_RET(dev_id, -EINVAL); |
| 714 | dev = &rte_eventdevs[dev_id]; |
| 715 | |
| 716 | if (!is_valid_port(dev, port_id)) { |
| 717 | RTE_EDEV_LOG_ERR("Invalid port_id=%" PRIu8, port_id); |
| 718 | return -EINVAL; |
| 719 | } |
| 720 | |
| 721 | /* Check new_event_threshold limit */ |
| 722 | if ((port_conf && !port_conf->new_event_threshold) || |
| 723 | (port_conf && port_conf->new_event_threshold > |
| 724 | dev->data->dev_conf.nb_events_limit)) { |
| 725 | RTE_EDEV_LOG_ERR( |
| 726 | "dev%d port%d Invalid event_threshold=%d nb_events_limit=%d", |
| 727 | dev_id, port_id, port_conf->new_event_threshold, |
| 728 | dev->data->dev_conf.nb_events_limit); |
| 729 | return -EINVAL; |
| 730 | } |
| 731 | |
| 732 | /* Check dequeue_depth limit */ |
| 733 | if ((port_conf && !port_conf->dequeue_depth) || |
| 734 | (port_conf && port_conf->dequeue_depth > |
| 735 | dev->data->dev_conf.nb_event_port_dequeue_depth)) { |
| 736 | RTE_EDEV_LOG_ERR( |
| 737 | "dev%d port%d Invalid dequeue depth=%d max_dequeue_depth=%d", |
| 738 | dev_id, port_id, port_conf->dequeue_depth, |
| 739 | dev->data->dev_conf.nb_event_port_dequeue_depth); |
| 740 | return -EINVAL; |
| 741 | } |
| 742 | |
| 743 | /* Check enqueue_depth limit */ |
| 744 | if ((port_conf && !port_conf->enqueue_depth) || |
| 745 | (port_conf && port_conf->enqueue_depth > |
| 746 | dev->data->dev_conf.nb_event_port_enqueue_depth)) { |
| 747 | RTE_EDEV_LOG_ERR( |
| 748 | "dev%d port%d Invalid enqueue depth=%d max_enqueue_depth=%d", |
| 749 | dev_id, port_id, port_conf->enqueue_depth, |
| 750 | dev->data->dev_conf.nb_event_port_enqueue_depth); |
| 751 | return -EINVAL; |
| 752 | } |
| 753 | |
| 754 | if (port_conf && |
| 755 | (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL) && |
| 756 | !(dev->data->event_dev_cap & |
| 757 | RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE)) { |
| 758 | RTE_EDEV_LOG_ERR( |
| 759 | "dev%d port%d Implicit release disable not supported", |
| 760 | dev_id, port_id); |
| 761 | return -EINVAL; |
| 762 | } |