| 555 | } |
| 556 | |
| 557 | static void |
| 558 | event_buffer_flush(struct event_buffer *bufp, uint8_t dev_id, uint8_t port_id, |
| 559 | uint16_t *nb_events_flushed, |
| 560 | uint16_t *nb_events_inv) |
| 561 | { |
| 562 | struct rte_event *events = bufp->events; |
| 563 | size_t head_idx, tail_idx; |
| 564 | uint16_t n = 0; |
| 565 | |
| 566 | /* Instead of modulus, bitwise AND with mask to get index. */ |
| 567 | head_idx = bufp->head & EVENT_BUFFER_MASK; |
| 568 | tail_idx = bufp->tail & EVENT_BUFFER_MASK; |
| 569 | |
| 570 | RTE_ASSERT(head_idx < EVENT_BUFFER_SZ && tail_idx < EVENT_BUFFER_SZ); |
| 571 | |
| 572 | /* Determine the largest contiguous run we can attempt to enqueue to the |
| 573 | * event device. |
| 574 | */ |
| 575 | if (head_idx > tail_idx) |
| 576 | n = head_idx - tail_idx; |
| 577 | else if (head_idx < tail_idx) |
| 578 | n = EVENT_BUFFER_SZ - tail_idx; |
| 579 | else if (event_buffer_full(bufp)) |
| 580 | n = EVENT_BUFFER_SZ - tail_idx; |
| 581 | else { |
| 582 | *nb_events_flushed = 0; |
| 583 | return; |
| 584 | } |
| 585 | |
| 586 | n = RTE_MIN(EVENT_BUFFER_BATCHSZ, n); |
| 587 | *nb_events_inv = 0; |
| 588 | |
| 589 | *nb_events_flushed = rte_event_enqueue_burst(dev_id, port_id, |
| 590 | &events[tail_idx], n); |
| 591 | if (*nb_events_flushed != n) { |
| 592 | if (rte_errno == EINVAL) { |
| 593 | EVTIM_LOG_ERR("failed to enqueue invalid event - " |
| 594 | "dropping it"); |
| 595 | (*nb_events_inv)++; |
| 596 | } else if (rte_errno == ENOSPC) |
| 597 | rte_pause(); |
| 598 | } |
| 599 | |
| 600 | if (*nb_events_flushed > 0) |
| 601 | EVTIM_BUF_LOG_DBG("enqueued %"PRIu16" timer events to event " |
| 602 | "device", *nb_events_flushed); |
| 603 | |
| 604 | bufp->tail = bufp->tail + *nb_events_flushed + *nb_events_inv; |
| 605 | } |
| 606 | |
| 607 | /* |
| 608 | * Software event timer adapter implementation |
no test coverage detected