| 74 | } |
| 75 | |
| 76 | int |
| 77 | power_manager_init(void) |
| 78 | { |
| 79 | unsigned int i, num_cpus = 0, num_freqs = 0; |
| 80 | int ret = 0; |
| 81 | struct core_info *ci; |
| 82 | unsigned int max_core_num; |
| 83 | |
| 84 | rte_power_set_env(PM_ENV_NOT_SET); |
| 85 | |
| 86 | ci = get_core_info(); |
| 87 | if (!ci) { |
| 88 | RTE_LOG(ERR, POWER_MANAGER, |
| 89 | "Failed to get core info!\n"); |
| 90 | return -1; |
| 91 | } |
| 92 | |
| 93 | if (ci->core_count > RTE_MAX_LCORE) |
| 94 | max_core_num = RTE_MAX_LCORE; |
| 95 | else |
| 96 | max_core_num = ci->core_count; |
| 97 | |
| 98 | for (i = 0; i < max_core_num; i++) { |
| 99 | if (rte_lcore_index(i) == -1) |
| 100 | continue; |
| 101 | |
| 102 | if (ci->cd[i].global_enabled_cpus) { |
| 103 | if (rte_power_init(i) < 0) |
| 104 | RTE_LOG(ERR, POWER_MANAGER, |
| 105 | "Unable to initialize power manager " |
| 106 | "for core %u\n", i); |
| 107 | num_cpus++; |
| 108 | num_freqs = rte_power_freqs(i, |
| 109 | global_core_freq_info[i].freqs, |
| 110 | RTE_MAX_LCORE_FREQS); |
| 111 | if (num_freqs == 0) { |
| 112 | RTE_LOG(ERR, POWER_MANAGER, |
| 113 | "Unable to get frequency list for core %u\n", |
| 114 | i); |
| 115 | ci->cd[i].oob_enabled = 0; |
| 116 | ret = -1; |
| 117 | } |
| 118 | global_core_freq_info[i].num_freqs = num_freqs; |
| 119 | |
| 120 | rte_spinlock_init(&global_core_freq_info[i].power_sl); |
| 121 | } |
| 122 | if (ci->cd[i].oob_enabled) |
| 123 | add_core_to_monitor(i); |
| 124 | } |
| 125 | RTE_LOG(INFO, POWER_MANAGER, "Managing %u cores out of %u available host cores\n", |
| 126 | num_cpus, ci->core_count); |
| 127 | return ret; |
| 128 | |
| 129 | } |
| 130 | |
| 131 | uint32_t |
| 132 | power_manager_get_current_frequency(unsigned core_num) |
no test coverage detected