| 168 | } |
| 169 | |
| 170 | static int |
| 171 | intel_ntb_dev_init(const struct rte_rawdev *dev) |
| 172 | { |
| 173 | struct ntb_hw *hw = dev->dev_private; |
| 174 | uint8_t bar; |
| 175 | int ret, i; |
| 176 | |
| 177 | if (hw == NULL) { |
| 178 | NTB_LOG(ERR, "Invalid device."); |
| 179 | return -EINVAL; |
| 180 | } |
| 181 | |
| 182 | hw->hw_addr = (char *)hw->pci_dev->mem_resource[0].addr; |
| 183 | |
| 184 | if (is_gen3_ntb(hw)) |
| 185 | ret = intel_ntb3_check_ppd(hw); |
| 186 | else if (is_gen4_ntb(hw)) |
| 187 | /* PPD is in MMIO but not config space for NTB Gen4 */ |
| 188 | ret = intel_ntb4_check_ppd(hw); |
| 189 | else { |
| 190 | NTB_LOG(ERR, "Cannot init device for unsupported device."); |
| 191 | return -ENOTSUP; |
| 192 | } |
| 193 | |
| 194 | if (ret) |
| 195 | return ret; |
| 196 | |
| 197 | hw->mw_cnt = XEON_MW_COUNT; |
| 198 | hw->db_cnt = XEON_DB_COUNT; |
| 199 | hw->spad_cnt = XEON_SPAD_COUNT; |
| 200 | |
| 201 | hw->mw_size = rte_zmalloc("ntb_mw_size", |
| 202 | hw->mw_cnt * sizeof(uint64_t), 0); |
| 203 | if (hw->mw_size == NULL) { |
| 204 | NTB_LOG(ERR, "Cannot allocate memory for mw size."); |
| 205 | return -ENOMEM; |
| 206 | } |
| 207 | |
| 208 | for (i = 0; i < hw->mw_cnt; i++) { |
| 209 | bar = intel_ntb_bar[i]; |
| 210 | hw->mw_size[i] = hw->pci_dev->mem_resource[bar].len; |
| 211 | } |
| 212 | |
| 213 | /* Reserve the last 2 spad registers for users. */ |
| 214 | for (i = 0; i < NTB_SPAD_USER_MAX_NUM; i++) |
| 215 | hw->spad_user_list[i] = hw->spad_cnt; |
| 216 | hw->spad_user_list[0] = hw->spad_cnt - 2; |
| 217 | hw->spad_user_list[1] = hw->spad_cnt - 1; |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | static void * |
| 223 | intel_ntb_get_peer_mw_addr(const struct rte_rawdev *dev, int mw_idx) |
nothing calls this directly
no test coverage detected