| 553 | } |
| 554 | |
| 555 | static int init_max10_device_table(struct intel_max10_device *max10) |
| 556 | { |
| 557 | struct altera_spi_device *spi = NULL; |
| 558 | struct max10_compatible_id *id; |
| 559 | struct fdt_header hdr; |
| 560 | char *fdt_root = NULL; |
| 561 | u32 dtb_magic = 0; |
| 562 | u32 dt_size, dt_addr, val; |
| 563 | int ret = 0; |
| 564 | |
| 565 | spi = (struct altera_spi_device *)max10->spi_master; |
| 566 | if (!spi) { |
| 567 | dev_err(max10, "spi master is not set\n"); |
| 568 | return -EINVAL; |
| 569 | } |
| 570 | if (spi->dtb) |
| 571 | dtb_magic = *(u32 *)spi->dtb; |
| 572 | |
| 573 | if (dtb_magic != 0xEDFE0DD0) { |
| 574 | dev_info(max10, "read DTB from NOR flash\n"); |
| 575 | ret = max10_sys_read(max10, DT_AVAIL_REG, &val); |
| 576 | if (ret) { |
| 577 | dev_err(max10 "cannot read DT_AVAIL_REG\n"); |
| 578 | return ret; |
| 579 | } |
| 580 | |
| 581 | if (!(val & DT_AVAIL)) { |
| 582 | dev_err(max10 "DT not available\n"); |
| 583 | return -EINVAL; |
| 584 | } |
| 585 | |
| 586 | ret = max10_sys_read(max10, DT_BASE_ADDR_REG, &dt_addr); |
| 587 | if (ret) { |
| 588 | dev_info(max10 "cannot get base addr of device table\n"); |
| 589 | return ret; |
| 590 | } |
| 591 | |
| 592 | ret = enable_nor_flash(max10, true); |
| 593 | if (ret) { |
| 594 | dev_err(max10 "fail to enable flash\n"); |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | ret = altera_nor_flash_read(max10, dt_addr, &hdr, sizeof(hdr)); |
| 599 | if (ret) { |
| 600 | dev_err(max10 "read fdt header fail\n"); |
| 601 | goto disable_nor_flash; |
| 602 | } |
| 603 | |
| 604 | ret = fdt_check_header(&hdr); |
| 605 | if (ret) { |
| 606 | dev_err(max10 "check fdt header fail\n"); |
| 607 | goto disable_nor_flash; |
| 608 | } |
| 609 | |
| 610 | dt_size = fdt_totalsize(&hdr); |
| 611 | if (dt_size > DFT_MAX_SIZE) { |
| 612 | dev_err(max10 "invalid device table size\n"); |
no test coverage detected