| 54 | } |
| 55 | |
| 56 | static int poll_timeout(struct intel_max10_device *dev, uint32_t offset, |
| 57 | bool (*cond)(uint32_t), uint32_t interval_ms, uint32_t timeout_ms) |
| 58 | { |
| 59 | uint32_t val = 0; |
| 60 | int ret = 0; |
| 61 | |
| 62 | for (;;) { |
| 63 | ret = max10_sys_read(dev, offset, &val); |
| 64 | if (ret < 0) { |
| 65 | dev_err(dev, |
| 66 | "Failed to read max10 register 0x%x [e:%d]\n", |
| 67 | offset, ret); |
| 68 | break; |
| 69 | } |
| 70 | |
| 71 | if (cond(val)) { |
| 72 | dev_debug(dev, |
| 73 | "Read 0x%08x from max10 register 0x%x " |
| 74 | "[poll success]\n", val, offset); |
| 75 | ret = 0; |
| 76 | break; |
| 77 | } |
| 78 | if (timeout_ms > interval_ms) |
| 79 | timeout_ms -= interval_ms; |
| 80 | else |
| 81 | timeout_ms = 0; |
| 82 | if (timeout_ms == 0) { |
| 83 | dev_debug(dev, |
| 84 | "Read 0x%08x from max10 register 0x%x " |
| 85 | "[poll timeout]\n", val, offset); |
| 86 | ret = -ETIMEDOUT; |
| 87 | break; |
| 88 | } |
| 89 | msleep(interval_ms); |
| 90 | } |
| 91 | |
| 92 | return ret; |
| 93 | } |
| 94 | |
| 95 | static int n3000_secure_update_start(struct intel_max10_device *dev) |
| 96 | { |
no test coverage detected