| 382 | } |
| 383 | |
| 384 | static int ase_write_unaligned(struct dma_afu_ctx *ctx, uint64_t dev_addr, |
| 385 | uint64_t host_addr, uint32_t count) |
| 386 | { |
| 387 | uint64_t dev_aligned_addr = 0; |
| 388 | uint64_t shift = 0; |
| 389 | uint64_t val = 0; |
| 390 | uintptr_t addr = (uintptr_t)host_addr; /* transfer to pointer size */ |
| 391 | |
| 392 | IFPGA_RAWDEV_PMD_DEBUG("0x%"PRIx64" --> 0x%"PRIx64" (0x%x)", host_addr, |
| 393 | dev_addr, count); |
| 394 | |
| 395 | if (!ctx || (count >= QWORD_BYTES)) |
| 396 | return -EINVAL; |
| 397 | |
| 398 | if (!count) |
| 399 | return 0; |
| 400 | |
| 401 | switch_ase_page(ctx, dev_addr); |
| 402 | |
| 403 | shift = dev_addr % QWORD_BYTES; |
| 404 | dev_aligned_addr = (dev_addr - shift) & DMA_ASE_WINDOW_MASK; |
| 405 | val = rte_read64(ctx->ase_data_addr + dev_aligned_addr); |
| 406 | rte_memcpy(((char *)(&val)) + shift, (void *)addr, count); |
| 407 | |
| 408 | /* write back to device */ |
| 409 | rte_write64(val, ctx->ase_data_addr + dev_aligned_addr); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static int ase_write(struct dma_afu_ctx *ctx, uint64_t *dst_ptr, |
| 415 | uint64_t *src_ptr, uint64_t *count) |
no test coverage detected