| 202 | } |
| 203 | |
| 204 | int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev) |
| 205 | { |
| 206 | uint32_t vtctl, fcrth; |
| 207 | uint32_t vfre_slot, vfre_offset; |
| 208 | uint16_t vf_num; |
| 209 | const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ |
| 210 | const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); |
| 211 | struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); |
| 212 | uint32_t gpie; |
| 213 | uint32_t gcr_ext; |
| 214 | uint32_t vlanctrl; |
| 215 | int i; |
| 216 | |
| 217 | vf_num = dev_num_vf(eth_dev); |
| 218 | if (vf_num == 0) |
| 219 | return -1; |
| 220 | |
| 221 | /* enable VMDq and set the default pool for PF */ |
| 222 | vtctl = rd32(hw, TXGBE_POOLCTL); |
| 223 | vtctl &= ~TXGBE_POOLCTL_DEFPL_MASK; |
| 224 | vtctl |= TXGBE_POOLCTL_DEFPL(RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); |
| 225 | vtctl |= TXGBE_POOLCTL_RPLEN; |
| 226 | wr32(hw, TXGBE_POOLCTL, vtctl); |
| 227 | |
| 228 | vfre_offset = vf_num & VFRE_MASK; |
| 229 | vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0; |
| 230 | |
| 231 | /* Enable pools reserved to PF only */ |
| 232 | wr32(hw, TXGBE_POOLRXENA(vfre_slot), (~0U) << vfre_offset); |
| 233 | wr32(hw, TXGBE_POOLRXENA(vfre_slot ^ 1), vfre_slot - 1); |
| 234 | wr32(hw, TXGBE_POOLTXENA(vfre_slot), (~0U) << vfre_offset); |
| 235 | wr32(hw, TXGBE_POOLTXENA(vfre_slot ^ 1), vfre_slot - 1); |
| 236 | |
| 237 | wr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA); |
| 238 | |
| 239 | /* clear VMDq map to permanent rar 0 */ |
| 240 | hw->mac.clear_vmdq(hw, 0, BIT_MASK32); |
| 241 | |
| 242 | /* clear VMDq map to scan rar 127 */ |
| 243 | wr32(hw, TXGBE_ETHADDRIDX, hw->mac.num_rar_entries); |
| 244 | wr32(hw, TXGBE_ETHADDRASSL, 0); |
| 245 | wr32(hw, TXGBE_ETHADDRASSH, 0); |
| 246 | |
| 247 | /* set VMDq map to default PF pool */ |
| 248 | hw->mac.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); |
| 249 | |
| 250 | /* |
| 251 | * SW msut set PORTCTL.VT_Mode the same as GPIE.VT_Mode |
| 252 | */ |
| 253 | gpie = rd32(hw, TXGBE_GPIE); |
| 254 | gpie |= TXGBE_GPIE_MSIX; |
| 255 | gcr_ext = rd32(hw, TXGBE_PORTCTL); |
| 256 | gcr_ext &= ~TXGBE_PORTCTL_NUMVT_MASK; |
| 257 | |
| 258 | switch (RTE_ETH_DEV_SRIOV(eth_dev).active) { |
| 259 | case RTE_ETH_64_POOLS: |
| 260 | gcr_ext |= TXGBE_PORTCTL_NUMVT_64; |
| 261 | break; |
no test coverage detected