| 995 | } |
| 996 | |
| 997 | static void |
| 998 | txgbevf_configure_msix(struct rte_eth_dev *dev) |
| 999 | { |
| 1000 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 1001 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 1002 | struct txgbe_hw *hw = TXGBE_DEV_HW(dev); |
| 1003 | uint32_t q_idx; |
| 1004 | uint32_t vector_idx = TXGBE_MISC_VEC_ID; |
| 1005 | uint32_t base = TXGBE_MISC_VEC_ID; |
| 1006 | |
| 1007 | /* Configure VF other cause ivar */ |
| 1008 | txgbevf_set_ivar_map(hw, -1, 1, vector_idx); |
| 1009 | |
| 1010 | /* won't configure msix register if no mapping is done |
| 1011 | * between intr vector and event fd. |
| 1012 | */ |
| 1013 | if (!rte_intr_dp_is_en(intr_handle)) |
| 1014 | return; |
| 1015 | |
| 1016 | if (rte_intr_allow_others(intr_handle)) { |
| 1017 | base = TXGBE_RX_VEC_START; |
| 1018 | vector_idx = TXGBE_RX_VEC_START; |
| 1019 | } |
| 1020 | |
| 1021 | /* Configure all RX queues of VF */ |
| 1022 | for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { |
| 1023 | /* Force all queue use vector 0, |
| 1024 | * as TXGBE_VF_MAXMSIVECTOR = 1 |
| 1025 | */ |
| 1026 | txgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); |
| 1027 | rte_intr_vec_list_index_set(intr_handle, q_idx, |
| 1028 | vector_idx); |
| 1029 | if (vector_idx < base + rte_intr_nb_efd_get(intr_handle) |
| 1030 | - 1) |
| 1031 | vector_idx++; |
| 1032 | } |
| 1033 | |
| 1034 | /* As RX queue setting above show, all queues use the vector 0. |
| 1035 | * Set only the ITR value of TXGBE_MISC_VEC_ID. |
| 1036 | */ |
| 1037 | wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), |
| 1038 | TXGBE_ITR_IVAL(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) |
| 1039 | | TXGBE_ITR_WRDSA); |
| 1040 | } |
| 1041 | |
| 1042 | static int |
| 1043 | txgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, |
no test coverage detected