| 421 | } |
| 422 | |
| 423 | static void |
| 424 | txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) |
| 425 | { |
| 426 | int i; |
| 427 | u8 bwgp; |
| 428 | struct txgbe_dcb_tc_config *tc; |
| 429 | |
| 430 | UNREFERENCED_PARAMETER(hw); |
| 431 | |
| 432 | dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; |
| 433 | dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; |
| 434 | bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); |
| 435 | for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { |
| 436 | tc = &dcb_config->tc_config[i]; |
| 437 | tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; |
| 438 | tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); |
| 439 | tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; |
| 440 | tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); |
| 441 | tc->pfc = txgbe_dcb_pfc_disabled; |
| 442 | } |
| 443 | |
| 444 | /* Initialize default user to priority mapping, UPx->TC0 */ |
| 445 | tc = &dcb_config->tc_config[0]; |
| 446 | tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; |
| 447 | tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; |
| 448 | for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { |
| 449 | dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; |
| 450 | dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; |
| 451 | } |
| 452 | dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; |
| 453 | dcb_config->pfc_mode_enable = false; |
| 454 | dcb_config->vt_mode = true; |
| 455 | dcb_config->round_robin_enable = false; |
| 456 | /* support all DCB capabilities */ |
| 457 | dcb_config->support.capabilities = 0xFF; |
| 458 | } |
| 459 | |
| 460 | /* |
| 461 | * Ensure that all locks are released before first NVM or PHY access |
no outgoing calls
no test coverage detected