| 223 | } |
| 224 | |
| 225 | static s32 |
| 226 | txgbe_reset_extphy(struct txgbe_hw *hw) |
| 227 | { |
| 228 | u16 ctrl = 0; |
| 229 | int err, i; |
| 230 | |
| 231 | err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, |
| 232 | TXGBE_MD_DEV_GENERAL, &ctrl); |
| 233 | if (err != 0) |
| 234 | return err; |
| 235 | ctrl |= TXGBE_MD_PORT_CTRL_RESET; |
| 236 | err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL, |
| 237 | TXGBE_MD_DEV_GENERAL, ctrl); |
| 238 | if (err != 0) |
| 239 | return err; |
| 240 | |
| 241 | /* |
| 242 | * Poll for reset bit to self-clear indicating reset is complete. |
| 243 | * Some PHYs could take up to 3 seconds to complete and need about |
| 244 | * 1.7 usec delay after the reset is complete. |
| 245 | */ |
| 246 | for (i = 0; i < 30; i++) { |
| 247 | msec_delay(100); |
| 248 | err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, |
| 249 | TXGBE_MD_DEV_GENERAL, &ctrl); |
| 250 | if (err != 0) |
| 251 | return err; |
| 252 | |
| 253 | if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) { |
| 254 | usec_delay(2); |
| 255 | break; |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | if (ctrl & TXGBE_MD_PORT_CTRL_RESET) { |
| 260 | err = TXGBE_ERR_RESET_FAILED; |
| 261 | DEBUGOUT("PHY reset polling failed to complete."); |
| 262 | } |
| 263 | |
| 264 | return err; |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * txgbe_reset_phy - Performs a PHY reset |