| 109 | } |
| 110 | |
| 111 | static uint32_t |
| 112 | sfc_phy_cap_from_link_speeds(uint32_t speeds) |
| 113 | { |
| 114 | uint32_t phy_caps = 0; |
| 115 | |
| 116 | if (~speeds & RTE_ETH_LINK_SPEED_FIXED) { |
| 117 | phy_caps |= (1 << EFX_PHY_CAP_AN); |
| 118 | /* |
| 119 | * If no speeds are specified in the mask, any supported |
| 120 | * may be negotiated |
| 121 | */ |
| 122 | if (speeds == RTE_ETH_LINK_SPEED_AUTONEG) |
| 123 | phy_caps |= |
| 124 | (1 << EFX_PHY_CAP_1000FDX) | |
| 125 | (1 << EFX_PHY_CAP_10000FDX) | |
| 126 | (1 << EFX_PHY_CAP_25000FDX) | |
| 127 | (1 << EFX_PHY_CAP_40000FDX) | |
| 128 | (1 << EFX_PHY_CAP_50000FDX) | |
| 129 | (1 << EFX_PHY_CAP_100000FDX); |
| 130 | } |
| 131 | if (speeds & RTE_ETH_LINK_SPEED_1G) |
| 132 | phy_caps |= (1 << EFX_PHY_CAP_1000FDX); |
| 133 | if (speeds & RTE_ETH_LINK_SPEED_10G) |
| 134 | phy_caps |= (1 << EFX_PHY_CAP_10000FDX); |
| 135 | if (speeds & RTE_ETH_LINK_SPEED_25G) |
| 136 | phy_caps |= (1 << EFX_PHY_CAP_25000FDX); |
| 137 | if (speeds & RTE_ETH_LINK_SPEED_40G) |
| 138 | phy_caps |= (1 << EFX_PHY_CAP_40000FDX); |
| 139 | if (speeds & RTE_ETH_LINK_SPEED_50G) |
| 140 | phy_caps |= (1 << EFX_PHY_CAP_50000FDX); |
| 141 | if (speeds & RTE_ETH_LINK_SPEED_100G) |
| 142 | phy_caps |= (1 << EFX_PHY_CAP_100000FDX); |
| 143 | |
| 144 | return phy_caps; |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * Check requested device level configuration. |