Initializes the PFE library. * Must be called before using any of the library functions. * * @param[in] cbus_base CBUS virtual base address (as mapped in * the host CPU address space) * @param[in] ddr_base PFE DDR range virtual base address (as * mapped in the host CPU address space) * @param[in] ddr_phys_base PFE DDR range physical base address (as * mapped in platform) * @param[in] si
| 28 | * software) |
| 29 | */ |
| 30 | void |
| 31 | pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, |
| 32 | unsigned int size) |
| 33 | { |
| 34 | cbus_base_addr = cbus_base; |
| 35 | ddr_base_addr = ddr_base; |
| 36 | ddr_phys_base_addr = ddr_phys_base; |
| 37 | ddr_size = size; |
| 38 | |
| 39 | pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); |
| 40 | pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); |
| 41 | pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; |
| 42 | pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 43 | pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 44 | pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 45 | |
| 46 | pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); |
| 47 | pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); |
| 48 | pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; |
| 49 | pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 50 | pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 51 | pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 52 | |
| 53 | pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); |
| 54 | pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); |
| 55 | pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; |
| 56 | pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 57 | pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 58 | pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 59 | |
| 60 | pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); |
| 61 | pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); |
| 62 | pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; |
| 63 | pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 64 | pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 65 | pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 66 | |
| 67 | pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); |
| 68 | pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); |
| 69 | pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; |
| 70 | pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 71 | pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 72 | pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 73 | |
| 74 | pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); |
| 75 | pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); |
| 76 | pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; |
| 77 | pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; |
| 78 | pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; |
| 79 | pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; |
| 80 | |
| 81 | pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); |
| 82 | pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); |
| 83 | pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; |
| 84 | pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; |
| 85 | pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; |
| 86 | pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; |
| 87 |