Sets the configuration of a GPI block. * @param[in] base GPI base address * @param[in] cfg GPI configuration */
| 536 | * @param[in] cfg GPI configuration |
| 537 | */ |
| 538 | void |
| 539 | gpi_set_config(void *base, struct gpi_cfg *cfg) |
| 540 | { |
| 541 | writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base |
| 542 | + GPI_LMEM_ALLOC_ADDR); |
| 543 | writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base |
| 544 | + GPI_LMEM_FREE_ADDR); |
| 545 | writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base |
| 546 | + GPI_DDR_ALLOC_ADDR); |
| 547 | writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base |
| 548 | + GPI_DDR_FREE_ADDR); |
| 549 | writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); |
| 550 | writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); |
| 551 | writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); |
| 552 | writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); |
| 553 | writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); |
| 554 | writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); |
| 555 | writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); |
| 556 | |
| 557 | writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | |
| 558 | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); |
| 559 | writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); |
| 560 | writel(cfg->aseq_len, base + GPI_DTX_ASEQ); |
| 561 | writel(1, base + GPI_TOE_CHKSUM_EN); |
| 562 | |
| 563 | if (cfg->mtip_pause_reg) { |
| 564 | writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); |
| 565 | writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | /**************************** HIF ***************************/ |
| 570 | /* Initializes HIF copy block. |