| 279 | } |
| 280 | |
| 281 | static inline void |
| 282 | ngbe_vf_reset_msg(struct rte_eth_dev *eth_dev, uint16_t vf) |
| 283 | { |
| 284 | struct ngbe_hw *hw = ngbe_dev_hw(eth_dev); |
| 285 | uint32_t reg; |
| 286 | uint32_t vf_shift; |
| 287 | const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ |
| 288 | const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); |
| 289 | uint8_t nb_q_per_pool; |
| 290 | int i; |
| 291 | |
| 292 | vf_shift = vf & VFRE_MASK; |
| 293 | |
| 294 | /* enable transmit for vf */ |
| 295 | reg = rd32(hw, NGBE_POOLTXENA(0)); |
| 296 | reg |= (1 << vf_shift); |
| 297 | wr32(hw, NGBE_POOLTXENA(0), reg); |
| 298 | |
| 299 | /* enable all queue drop for IOV */ |
| 300 | nb_q_per_pool = RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool; |
| 301 | for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) { |
| 302 | ngbe_flush(hw); |
| 303 | reg = 1 << (i % 32); |
| 304 | wr32m(hw, NGBE_QPRXDROP, reg, reg); |
| 305 | } |
| 306 | |
| 307 | /* enable receive for vf */ |
| 308 | reg = rd32(hw, NGBE_POOLRXENA(0)); |
| 309 | reg |= (reg | (1 << vf_shift)); |
| 310 | wr32(hw, NGBE_POOLRXENA(0), reg); |
| 311 | |
| 312 | ngbe_vf_reset_event(eth_dev, vf); |
| 313 | } |
| 314 | |
| 315 | static int |
| 316 | ngbe_disable_vf_mc_promisc(struct rte_eth_dev *eth_dev, uint32_t vf) |
no test coverage detected