* Set the IVAR registers, mapping interrupt causes to vectors * @param hw * pointer to ngbe_hw struct * @direction * 0 for Rx, 1 for Tx, -1 for other causes * @queue * queue to map the corresponding interrupt to * @msix_vector * the vector to map to the corresponding queue */
| 2761 | * the vector to map to the corresponding queue |
| 2762 | */ |
| 2763 | void |
| 2764 | ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction, |
| 2765 | uint8_t queue, uint8_t msix_vector) |
| 2766 | { |
| 2767 | uint32_t tmp, idx; |
| 2768 | |
| 2769 | if (direction == -1) { |
| 2770 | /* other causes */ |
| 2771 | msix_vector |= NGBE_IVARMISC_VLD; |
| 2772 | idx = 0; |
| 2773 | tmp = rd32(hw, NGBE_IVARMISC); |
| 2774 | tmp &= ~(0xFF << idx); |
| 2775 | tmp |= (msix_vector << idx); |
| 2776 | wr32(hw, NGBE_IVARMISC, tmp); |
| 2777 | } else { |
| 2778 | /* rx or tx causes */ |
| 2779 | /* Workaround for ICR lost */ |
| 2780 | idx = ((16 * (queue & 1)) + (8 * direction)); |
| 2781 | tmp = rd32(hw, NGBE_IVAR(queue >> 1)); |
| 2782 | tmp &= ~(0xFF << idx); |
| 2783 | tmp |= (msix_vector << idx); |
| 2784 | wr32(hw, NGBE_IVAR(queue >> 1), tmp); |
| 2785 | } |
| 2786 | } |
| 2787 | |
| 2788 | /** |
| 2789 | * Sets up the hardware to properly generate MSI-X interrupts |
no test coverage detected