* It reads ICR and sets flag for the link_update. * * @param dev * Pointer to struct rte_eth_dev. * * @return * - On success, zero. * - On failure, a negative value. */
| 2154 | * - On failure, a negative value. |
| 2155 | */ |
| 2156 | static int |
| 2157 | ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev) |
| 2158 | { |
| 2159 | uint32_t eicr; |
| 2160 | struct ngbe_hw *hw = ngbe_dev_hw(dev); |
| 2161 | struct ngbe_interrupt *intr = ngbe_dev_intr(dev); |
| 2162 | |
| 2163 | eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_VEC0]; |
| 2164 | if (!eicr) { |
| 2165 | /* |
| 2166 | * shared interrupt alert! |
| 2167 | * make sure interrupts are enabled because the read will |
| 2168 | * have disabled interrupts. |
| 2169 | */ |
| 2170 | if (!hw->adapter_stopped) |
| 2171 | ngbe_enable_intr(dev); |
| 2172 | return 0; |
| 2173 | } |
| 2174 | ((u32 *)hw->isb_mem)[NGBE_ISB_VEC0] = 0; |
| 2175 | |
| 2176 | /* read-on-clear nic registers here */ |
| 2177 | eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC]; |
| 2178 | PMD_DRV_LOG(DEBUG, "eicr %x", eicr); |
| 2179 | |
| 2180 | intr->flags = 0; |
| 2181 | |
| 2182 | /* set flag for async link update */ |
| 2183 | if (eicr & NGBE_ICRMISC_PHY) |
| 2184 | intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; |
| 2185 | |
| 2186 | if (eicr & NGBE_ICRMISC_VFMBX) |
| 2187 | intr->flags |= NGBE_FLAG_MAILBOX; |
| 2188 | |
| 2189 | if (eicr & NGBE_ICRMISC_LNKSEC) |
| 2190 | intr->flags |= NGBE_FLAG_MACSEC; |
| 2191 | |
| 2192 | if (eicr & NGBE_ICRMISC_GPIO) |
| 2193 | intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; |
| 2194 | |
| 2195 | if (eicr & NGBE_ICRMISC_HEAT) |
| 2196 | intr->flags |= NGBE_FLAG_OVERHEAT; |
| 2197 | |
| 2198 | ((u32 *)hw->isb_mem)[NGBE_ISB_MISC] = 0; |
| 2199 | |
| 2200 | return 0; |
| 2201 | } |
| 2202 | |
| 2203 | /** |
| 2204 | * It gets and then prints the link status. |
no test coverage detected