* Reset and stop device. */
| 1245 | * Reset and stop device. |
| 1246 | */ |
| 1247 | static int |
| 1248 | ngbe_dev_close(struct rte_eth_dev *dev) |
| 1249 | { |
| 1250 | struct ngbe_hw *hw = ngbe_dev_hw(dev); |
| 1251 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 1252 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 1253 | int retries = 0; |
| 1254 | int ret; |
| 1255 | |
| 1256 | PMD_INIT_FUNC_TRACE(); |
| 1257 | |
| 1258 | if (rte_eal_process_type() != RTE_PROC_PRIMARY) |
| 1259 | return 0; |
| 1260 | |
| 1261 | ngbe_pf_reset_hw(hw); |
| 1262 | |
| 1263 | ngbe_dev_stop(dev); |
| 1264 | |
| 1265 | /* Let firmware take over control of hardware */ |
| 1266 | wr32m(hw, NGBE_PORTCTL, NGBE_PORTCTL_DRVLOAD, 0); |
| 1267 | |
| 1268 | ngbe_dev_free_queues(dev); |
| 1269 | |
| 1270 | ngbe_set_pcie_master(hw, false); |
| 1271 | |
| 1272 | /* reprogram the RAR[0] in case user changed it. */ |
| 1273 | ngbe_set_rar(hw, 0, hw->mac.addr, 0, true); |
| 1274 | |
| 1275 | /* Unlock any pending hardware semaphore */ |
| 1276 | ngbe_swfw_lock_reset(hw); |
| 1277 | |
| 1278 | /* disable uio intr before callback unregister */ |
| 1279 | rte_intr_disable(intr_handle); |
| 1280 | |
| 1281 | do { |
| 1282 | ret = rte_intr_callback_unregister(intr_handle, |
| 1283 | ngbe_dev_interrupt_handler, dev); |
| 1284 | if (ret >= 0 || ret == -ENOENT) { |
| 1285 | break; |
| 1286 | } else if (ret != -EAGAIN) { |
| 1287 | PMD_INIT_LOG(ERR, |
| 1288 | "intr callback unregister failed: %d", |
| 1289 | ret); |
| 1290 | } |
| 1291 | rte_delay_ms(100); |
| 1292 | } while (retries++ < (10 + NGBE_LINK_UP_TIME)); |
| 1293 | |
| 1294 | /* uninitialize PF if max_vfs not zero */ |
| 1295 | ngbe_pf_host_uninit(dev); |
| 1296 | |
| 1297 | rte_free(dev->data->mac_addrs); |
| 1298 | dev->data->mac_addrs = NULL; |
| 1299 | |
| 1300 | rte_free(dev->data->hash_mac_addrs); |
| 1301 | dev->data->hash_mac_addrs = NULL; |
| 1302 | |
| 1303 | return ret; |
| 1304 | } |
no test coverage detected