| 113 | } |
| 114 | |
| 115 | s32 ngbe_init_phy_rtl(struct ngbe_hw *hw) |
| 116 | { |
| 117 | int i; |
| 118 | u16 value = 0; |
| 119 | |
| 120 | hw->init_phy = true; |
| 121 | msec_delay(1); |
| 122 | |
| 123 | hw->phy.set_phy_power(hw, true); |
| 124 | |
| 125 | for (i = 0; i < 15; i++) { |
| 126 | if (!rd32m(hw, NGBE_STAT, |
| 127 | NGBE_STAT_GPHY_IN_RST(hw->bus.lan_id))) |
| 128 | break; |
| 129 | |
| 130 | msec_delay(10); |
| 131 | } |
| 132 | if (i == 15) { |
| 133 | DEBUGOUT("GPhy reset exceeds maximum times."); |
| 134 | return NGBE_ERR_PHY_TIMEOUT; |
| 135 | } |
| 136 | |
| 137 | ngbe_efuse_calibration(hw); |
| 138 | |
| 139 | hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE); |
| 140 | hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value); |
| 141 | if (!(value & RTL_SCR_EFUSE)) { |
| 142 | DEBUGOUT("Write EFUSE failed."); |
| 143 | return NGBE_ERR_PHY_TIMEOUT; |
| 144 | } |
| 145 | |
| 146 | ngbe_wait_mdio_access_on(hw); |
| 147 | |
| 148 | hw->phy.write_reg(hw, 27, 0xa42, 0x8011); |
| 149 | hw->phy.write_reg(hw, 28, 0xa42, 0x5737); |
| 150 | |
| 151 | /* Disable fall to 100m if signal is not good */ |
| 152 | hw->phy.read_reg(hw, 17, 0xa44, &value); |
| 153 | value &= ~0x8; |
| 154 | hw->phy.write_reg(hw, 17, 0xa44, value); |
| 155 | |
| 156 | hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EXTINI); |
| 157 | hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value); |
| 158 | if (!(value & RTL_SCR_EXTINI)) { |
| 159 | DEBUGOUT("Write EXIINI failed."); |
| 160 | return NGBE_ERR_PHY_TIMEOUT; |
| 161 | } |
| 162 | |
| 163 | ngbe_wait_mdio_access_on(hw); |
| 164 | |
| 165 | for (i = 0; i < 100; i++) { |
| 166 | hw->phy.read_reg(hw, RTL_GSR, 0xa42, &value); |
| 167 | if ((value & RTL_GSR_ST) == RTL_GSR_ST_LANON) |
| 168 | break; |
| 169 | msec_delay(1); |
| 170 | } |
| 171 | if (i == 100) |
| 172 | return NGBE_ERR_PHY_TIMEOUT; |
nothing calls this directly
no test coverage detected