Invoked periodically on Rearm Queue completions. */
| 711 | |
| 712 | /* Invoked periodically on Rearm Queue completions. */ |
| 713 | void |
| 714 | mlx5_txpp_interrupt_handler(void *cb_arg) |
| 715 | { |
| 716 | #ifndef HAVE_IBV_DEVX_EVENT |
| 717 | RTE_SET_USED(cb_arg); |
| 718 | return; |
| 719 | #else |
| 720 | struct mlx5_dev_ctx_shared *sh = cb_arg; |
| 721 | union { |
| 722 | struct mlx5dv_devx_async_event_hdr event_resp; |
| 723 | uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128]; |
| 724 | } out; |
| 725 | |
| 726 | MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); |
| 727 | /* Process events in the loop. Only rearm completions are expected. */ |
| 728 | while (mlx5_glue->devx_get_event |
| 729 | (sh->txpp.echan, |
| 730 | &out.event_resp, |
| 731 | sizeof(out.buf)) >= |
| 732 | (ssize_t)sizeof(out.event_resp.cookie)) { |
| 733 | mlx5_txpp_handle_rearm_queue(sh); |
| 734 | mlx5_txpp_handle_clock_queue(sh); |
| 735 | mlx5_txpp_cq_arm(sh); |
| 736 | mlx5_txpp_doorbell_rearm_queue |
| 737 | (sh, sh->txpp.rearm_queue.sq_ci - 1); |
| 738 | } |
| 739 | #endif /* HAVE_IBV_DEVX_ASYNC */ |
| 740 | } |
| 741 | |
| 742 | static void |
| 743 | mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh) |
nothing calls this directly
no test coverage detected