| 512 | #endif |
| 513 | |
| 514 | static inline void |
| 515 | mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts) |
| 516 | { |
| 517 | /* |
| 518 | * The only CQE of Clock Queue is being continuously |
| 519 | * updated by hardware with specified rate. We must |
| 520 | * read timestamp and WQE completion index atomically. |
| 521 | */ |
| 522 | #if defined(RTE_ARCH_X86_64) |
| 523 | rte_int128_t src; |
| 524 | |
| 525 | memset(&src, 0, sizeof(src)); |
| 526 | *ts = src; |
| 527 | /* if (*from == *ts) *from = *src else *ts = *from; */ |
| 528 | mlx5_atomic128_compare_exchange(from, ts, &src); |
| 529 | #else |
| 530 | uint64_t *cqe = (uint64_t *)from; |
| 531 | |
| 532 | /* |
| 533 | * Power architecture does not support 16B compare-and-swap. |
| 534 | * ARM implements it in software, code below is more relevant. |
| 535 | */ |
| 536 | for (;;) { |
| 537 | uint64_t tm, op; |
| 538 | uint64_t *ps; |
| 539 | |
| 540 | rte_compiler_barrier(); |
| 541 | tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED); |
| 542 | op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED); |
| 543 | rte_compiler_barrier(); |
| 544 | if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED)) |
| 545 | continue; |
| 546 | if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED)) |
| 547 | continue; |
| 548 | ps = (uint64_t *)ts; |
| 549 | ps[0] = tm; |
| 550 | ps[1] = op; |
| 551 | return; |
| 552 | } |
| 553 | #endif |
| 554 | } |
| 555 | |
| 556 | /* Stores timestamp in the cache structure to share data with datapath. */ |
| 557 | static inline void |
no test coverage detected