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Function mlx5_tx_burst_empw_inline

dpdk/drivers/net/mlx5/mlx5_tx.h:2896–3197  ·  view source on GitHub ↗

* The routine sends packets with MLX5_OPCODE_EMPW * with inlining, optionally supports VLAN insertion. */

Source from the content-addressed store, hash-verified

2894 * with inlining, optionally supports VLAN insertion.
2895 */
2896static __rte_always_inline enum mlx5_txcmp_code
2897mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
2898 struct rte_mbuf **__rte_restrict pkts,
2899 unsigned int pkts_n,
2900 struct mlx5_txq_local *__rte_restrict loc,
2901 unsigned int olx)
2902{
2903 /*
2904 * Subroutine is the part of mlx5_tx_burst_single() and sends
2905 * single-segment packet with eMPW opcode with data inlining.
2906 */
2907 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
2908 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
2909 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
2910 MLX5_ASSERT(pkts_n > loc->pkts_sent);
2911 pkts += loc->pkts_sent + 1;
2912 pkts_n -= loc->pkts_sent;
2913 for (;;) {
2914 struct mlx5_wqe_dseg *__rte_restrict dseg;
2915 struct mlx5_wqe *__rte_restrict wqem;
2916 enum mlx5_txcmp_code ret;
2917 unsigned int room, part, nlim;
2918 unsigned int slen = 0;
2919
2920 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
2921 /*
2922 * Limits the amount of packets in one WQE
2923 * to improve CQE latency generation.
2924 */
2925 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
2926 MLX5_MPW_INLINE_MAX_PACKETS :
2927 MLX5_EMPW_MAX_PACKETS);
2928 if (MLX5_TXOFF_CONFIG(TXPP)) {
2929 enum mlx5_txcmp_code wret;
2930
2931 /* Generate WAIT for scheduling if requested. */
2932 wret = mlx5_tx_schedule_send(txq, loc, nlim, olx);
2933 if (wret == MLX5_TXCMP_CODE_EXIT)
2934 return MLX5_TXCMP_CODE_EXIT;
2935 if (wret == MLX5_TXCMP_CODE_ERROR)
2936 return MLX5_TXCMP_CODE_ERROR;
2937 }
2938 /* Check whether we have minimal amount WQEs */
2939 if (unlikely(loc->wqe_free <
2940 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
2941 return MLX5_TXCMP_CODE_EXIT;
2942 if (likely(pkts_n > 1))
2943 rte_prefetch0(*pkts);
2944 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2945 /*
2946 * Build eMPW title WQEBB:
2947 * - Control Segment, eMPW opcode, zero DS
2948 * - Ethernet Segment, no inline
2949 */
2950 mlx5_tx_cseg_init(txq, loc, wqem, 0,
2951 MLX5_OPCODE_ENHANCED_MPSW, olx);
2952 mlx5_tx_eseg_none(txq, loc, wqem,
2953 olx & ~MLX5_TXOFF_CONFIG_VLAN);

Callers 1

mlx5_tx_burst_singleFunction · 0.85

Calls 10

mlx5_tx_schedule_sendFunction · 0.85
mlx5_tx_cseg_initFunction · 0.85
mlx5_tx_eseg_noneFunction · 0.85
mlx5_tx_idone_empwFunction · 0.85
mlx5_tx_dseg_vlanFunction · 0.85
mlx5_tx_dseg_empwFunction · 0.85
mlx5_tx_dseg_ptrFunction · 0.85
mlx5_tx_able_to_empwFunction · 0.85
mlx5_tx_match_empwFunction · 0.85
rte_prefetch0Function · 0.50

Tested by

no test coverage detected