* Enable traffic flows configured by control plane * * @param dev * Pointer to Ethernet device structure. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */
| 1558 | * 0 on success, a negative errno value otherwise and rte_errno is set. |
| 1559 | */ |
| 1560 | int |
| 1561 | mlx5_traffic_enable(struct rte_eth_dev *dev) |
| 1562 | { |
| 1563 | struct mlx5_priv *priv = dev->data->dev_private; |
| 1564 | struct rte_flow_item_eth bcast = { |
| 1565 | .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", |
| 1566 | }; |
| 1567 | struct rte_flow_item_eth ipv6_multi_spec = { |
| 1568 | .hdr.dst_addr.addr_bytes = "\x33\x33\x00\x00\x00\x00", |
| 1569 | }; |
| 1570 | struct rte_flow_item_eth ipv6_multi_mask = { |
| 1571 | .hdr.dst_addr.addr_bytes = "\xff\xff\x00\x00\x00\x00", |
| 1572 | }; |
| 1573 | struct rte_flow_item_eth unicast = { |
| 1574 | .hdr.src_addr.addr_bytes = "\x00\x00\x00\x00\x00\x00", |
| 1575 | }; |
| 1576 | struct rte_flow_item_eth unicast_mask = { |
| 1577 | .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", |
| 1578 | }; |
| 1579 | const unsigned int vlan_filter_n = priv->vlan_filter_n; |
| 1580 | const struct rte_ether_addr cmp = { |
| 1581 | .addr_bytes = "\x00\x00\x00\x00\x00\x00", |
| 1582 | }; |
| 1583 | unsigned int i; |
| 1584 | unsigned int j; |
| 1585 | int ret; |
| 1586 | |
| 1587 | #ifdef HAVE_MLX5_HWS_SUPPORT |
| 1588 | if (priv->sh->config.dv_flow_en == 2) |
| 1589 | return mlx5_traffic_enable_hws(dev); |
| 1590 | #endif |
| 1591 | /* |
| 1592 | * Hairpin txq default flow should be created no matter if it is |
| 1593 | * isolation mode. Or else all the packets to be sent will be sent |
| 1594 | * out directly without the TX flow actions, e.g. encapsulation. |
| 1595 | */ |
| 1596 | for (i = 0; i != priv->txqs_n; ++i) { |
| 1597 | struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i); |
| 1598 | if (!txq_ctrl) |
| 1599 | continue; |
| 1600 | /* Only Tx implicit mode requires the default Tx flow. */ |
| 1601 | if (txq_ctrl->is_hairpin && |
| 1602 | txq_ctrl->hairpin_conf.tx_explicit == 0 && |
| 1603 | txq_ctrl->hairpin_conf.peers[0].port == |
| 1604 | priv->dev_data->port_id) { |
| 1605 | ret = mlx5_ctrl_flow_source_queue(dev, |
| 1606 | mlx5_txq_get_sqn(txq_ctrl)); |
| 1607 | if (ret) { |
| 1608 | mlx5_txq_release(dev, i); |
| 1609 | goto error; |
| 1610 | } |
| 1611 | } |
| 1612 | if (priv->sh->config.dv_esw_en) { |
| 1613 | uint32_t q = mlx5_txq_get_sqn(txq_ctrl); |
| 1614 | |
| 1615 | if (mlx5_flow_create_devx_sq_miss_flow(dev, q) == 0) { |
| 1616 | mlx5_txq_release(dev, i); |
| 1617 | DRV_LOG(ERR, |
no test coverage detected