* Create flow table. * * The input item and action templates will be binded to the table. * Flow memory will also be allocated. Matcher will be created based * on the item template. Action will be translated to the dedicated * DR action if possible. * * @param[in] dev * Pointer to the rte_eth_dev structure. * @param[in] table_cfg * Pointer to the table configuration. * @param[in] it
| 4273 | * Table on success, NULL otherwise and rte_errno is set. |
| 4274 | */ |
| 4275 | static struct rte_flow_template_table * |
| 4276 | flow_hw_table_create(struct rte_eth_dev *dev, |
| 4277 | const struct mlx5_flow_template_table_cfg *table_cfg, |
| 4278 | struct rte_flow_pattern_template *item_templates[], |
| 4279 | uint8_t nb_item_templates, |
| 4280 | struct rte_flow_actions_template *action_templates[], |
| 4281 | uint8_t nb_action_templates, |
| 4282 | struct rte_flow_error *error) |
| 4283 | { |
| 4284 | struct rte_flow_error sub_error = { |
| 4285 | .type = RTE_FLOW_ERROR_TYPE_NONE, |
| 4286 | .cause = NULL, |
| 4287 | .message = NULL, |
| 4288 | }; |
| 4289 | struct mlx5_priv *priv = dev->data->dev_private; |
| 4290 | struct mlx5dr_matcher_attr matcher_attr = {0}; |
| 4291 | struct rte_flow_template_table *tbl = NULL; |
| 4292 | struct mlx5_flow_group *grp; |
| 4293 | struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE]; |
| 4294 | struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE]; |
| 4295 | const struct rte_flow_template_table_attr *attr = &table_cfg->attr; |
| 4296 | struct rte_flow_attr flow_attr = attr->flow_attr; |
| 4297 | struct mlx5_flow_cb_ctx ctx = { |
| 4298 | .dev = dev, |
| 4299 | .error = &sub_error, |
| 4300 | .data = &flow_attr, |
| 4301 | }; |
| 4302 | struct mlx5_indexed_pool_config cfg = { |
| 4303 | .size = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size(), |
| 4304 | .trunk_size = 1 << 12, |
| 4305 | .per_core_cache = 1 << 13, |
| 4306 | .need_lock = 1, |
| 4307 | .release_mem_en = !!priv->sh->config.reclaim_mode, |
| 4308 | .malloc = mlx5_malloc, |
| 4309 | .free = mlx5_free, |
| 4310 | .type = "mlx5_hw_table_flow", |
| 4311 | }; |
| 4312 | struct mlx5_list_entry *ge; |
| 4313 | uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE; |
| 4314 | uint32_t nb_flows = rte_align32pow2(attr->nb_flows); |
| 4315 | bool port_started = !!dev->data->dev_started; |
| 4316 | int err; |
| 4317 | |
| 4318 | /* HWS layer accepts only 1 item template with root table. */ |
| 4319 | if (!attr->flow_attr.group) |
| 4320 | max_tpl = 1; |
| 4321 | cfg.max_idx = nb_flows; |
| 4322 | /* For table has very limited flows, disable cache. */ |
| 4323 | if (nb_flows < cfg.trunk_size) { |
| 4324 | cfg.per_core_cache = 0; |
| 4325 | cfg.trunk_size = nb_flows; |
| 4326 | } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) { |
| 4327 | cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN; |
| 4328 | } |
| 4329 | /* Check if we requires too many templates. */ |
| 4330 | if (nb_item_templates > max_tpl || |
| 4331 | nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) { |
| 4332 | rte_errno = EINVAL; |
no test coverage detected