* DPDK callback to get information about the device. * * @param dev * Pointer to Ethernet device structure. * @param[out] info * Info structure output buffer. */
| 346 | * Info structure output buffer. |
| 347 | */ |
| 348 | int |
| 349 | mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) |
| 350 | { |
| 351 | struct mlx5_priv *priv = dev->data->dev_private; |
| 352 | unsigned int max; |
| 353 | uint16_t max_wqe; |
| 354 | |
| 355 | /* FIXME: we should ask the device for these values. */ |
| 356 | info->min_rx_bufsize = 32; |
| 357 | info->max_rx_pktlen = 65536; |
| 358 | info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; |
| 359 | /* |
| 360 | * Since we need one CQ per QP, the limit is the minimum number |
| 361 | * between the two values. |
| 362 | */ |
| 363 | max = RTE_MIN(priv->sh->dev_cap.max_cq, priv->sh->dev_cap.max_qp); |
| 364 | /* max_rx_queues is uint16_t. */ |
| 365 | max = RTE_MIN(max, (unsigned int)UINT16_MAX); |
| 366 | info->max_rx_queues = max; |
| 367 | info->max_tx_queues = max; |
| 368 | info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; |
| 369 | info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); |
| 370 | info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; |
| 371 | info->rx_seg_capa.multi_pools = !priv->config.mprq.enabled; |
| 372 | info->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled; |
| 373 | info->rx_seg_capa.offset_align_log2 = 0; |
| 374 | info->rx_offload_capa = (mlx5_get_rx_port_offloads() | |
| 375 | info->rx_queue_offload_capa); |
| 376 | info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); |
| 377 | info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; |
| 378 | info->if_index = mlx5_ifindex(dev); |
| 379 | info->reta_size = priv->reta_idx_n ? |
| 380 | priv->reta_idx_n : priv->sh->dev_cap.ind_table_max_size; |
| 381 | info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; |
| 382 | info->speed_capa = priv->link_speed_capa; |
| 383 | info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; |
| 384 | mlx5_set_default_params(dev, info); |
| 385 | mlx5_set_txlimit_params(dev, info); |
| 386 | max_wqe = mlx5_dev_get_max_wq_size(priv->sh); |
| 387 | info->rx_desc_lim.nb_max = max_wqe; |
| 388 | info->tx_desc_lim.nb_max = max_wqe; |
| 389 | if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && |
| 390 | priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) |
| 391 | info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; |
| 392 | info->switch_info.name = dev->data->name; |
| 393 | info->switch_info.domain_id = priv->domain_id; |
| 394 | info->switch_info.port_id = priv->representor_id; |
| 395 | info->switch_info.rx_domain = 0; /* No sub Rx domains. */ |
| 396 | if (priv->representor) { |
| 397 | uint16_t port_id; |
| 398 | |
| 399 | MLX5_ETH_FOREACH_DEV(port_id, dev->device) { |
| 400 | struct mlx5_priv *opriv = |
| 401 | rte_eth_devices[port_id].data->dev_private; |
| 402 | |
| 403 | if (!opriv || |
| 404 | opriv->representor || |
| 405 | opriv->sh != priv->sh || |
nothing calls this directly
no test coverage detected