* Set TIR attribute struct with relevant input values. * * @param[in] dev * Pointer to Ethernet device. * @param[in] rss_key * RSS key for the Rx hash queue. * @param[in] hash_fields * Verbs protocol hash field to make the RSS on. * @param[in] ind_tbl * Indirection table for TIR. If table queues array is NULL, * a TIR for drop queue is assumed. * @param[in] tunnel * Tunnel
| 808 | * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set. |
| 809 | */ |
| 810 | static void |
| 811 | mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, |
| 812 | uint64_t hash_fields, |
| 813 | const struct mlx5_ind_table_obj *ind_tbl, |
| 814 | int tunnel, bool symmetric_hash_function, |
| 815 | struct mlx5_devx_tir_attr *tir_attr) |
| 816 | { |
| 817 | struct mlx5_priv *priv = dev->data->dev_private; |
| 818 | bool is_hairpin; |
| 819 | bool lro = false; |
| 820 | uint32_t i; |
| 821 | |
| 822 | /* NULL queues designate drop queue. */ |
| 823 | if (ind_tbl->queues == NULL) { |
| 824 | is_hairpin = priv->drop_queue.rxq->ctrl->is_hairpin; |
| 825 | } else if (mlx5_is_external_rxq(dev, ind_tbl->queues[0])) { |
| 826 | /* External RxQ supports neither Hairpin nor LRO. */ |
| 827 | is_hairpin = false; |
| 828 | } else { |
| 829 | is_hairpin = mlx5_rxq_is_hairpin(dev, ind_tbl->queues[0]); |
| 830 | lro = true; |
| 831 | /* Enable TIR LRO only if all the queues were configured for. */ |
| 832 | for (i = 0; i < ind_tbl->queues_n; ++i) { |
| 833 | struct mlx5_rxq_data *rxq_i = |
| 834 | mlx5_rxq_data_get(dev, ind_tbl->queues[i]); |
| 835 | |
| 836 | if (rxq_i != NULL && !rxq_i->lro) { |
| 837 | lro = false; |
| 838 | break; |
| 839 | } |
| 840 | } |
| 841 | } |
| 842 | memset(tir_attr, 0, sizeof(*tir_attr)); |
| 843 | tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT; |
| 844 | tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ; |
| 845 | tir_attr->tunneled_offload_en = !!tunnel; |
| 846 | tir_attr->rx_hash_symmetric = symmetric_hash_function; |
| 847 | /* If needed, translate hash_fields bitmap to PRM format. */ |
| 848 | if (hash_fields) { |
| 849 | struct mlx5_rx_hash_field_select *rx_hash_field_select = |
| 850 | #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT |
| 851 | hash_fields & IBV_RX_HASH_INNER ? |
| 852 | &tir_attr->rx_hash_field_selector_inner : |
| 853 | #endif |
| 854 | &tir_attr->rx_hash_field_selector_outer; |
| 855 | /* 1 bit: 0: IPv4, 1: IPv6. */ |
| 856 | rx_hash_field_select->l3_prot_type = |
| 857 | !!(hash_fields & MLX5_IPV6_IBV_RX_HASH); |
| 858 | /* 1 bit: 0: TCP, 1: UDP. */ |
| 859 | rx_hash_field_select->l4_prot_type = |
| 860 | !!(hash_fields & MLX5_UDP_IBV_RX_HASH); |
| 861 | /* Bitmask which sets which fields to use in RX Hash. */ |
| 862 | rx_hash_field_select->selected_fields = |
| 863 | ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) << |
| 864 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) | |
| 865 | (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) << |
| 866 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP | |
| 867 | (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) << |
no test coverage detected